{"id":"https://openalex.org/W4231605148","doi":"https://doi.org/10.1109/date.2004.1269098","title":"Multi-processor SoC design methodology using a concept of two-layer hardware-dependent software","display_name":"Multi-processor SoC design methodology using a concept of two-layer hardware-dependent software","publication_year":2004,"publication_date":"2004-06-03","ids":{"openalex":"https://openalex.org/W4231605148","doi":"https://doi.org/10.1109/date.2004.1269098"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1269098","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269098","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063521444","display_name":"Sungjoo Yoo","orcid":"https://orcid.org/0000-0002-5853-0675"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Sungjoo Yoo","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103555042","display_name":"Mohamed-Wassim Youssef","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"M.-W. Youssef","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024567615","display_name":"A. Bouchhima","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"A. Bouchhima","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017673519","display_name":"A.A. Jerraya","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"A.A. Jerraya","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064420534","display_name":"M. Diaz-Nava","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"M. Diaz-Nava","raw_affiliation_strings":["STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7079,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.64565826,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1382","last_page":"1383"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.954800009727478,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9524000287055969,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.894150972366333},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7767665386199951},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.7114645838737488},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6560949087142944},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.6098834276199341},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5883833765983582},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.5812951922416687},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5079246163368225},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.49962902069091797},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.4941895306110382},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4702438414096832},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.4488270580768585},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.22734034061431885},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17932528257369995}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.894150972366333},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7767665386199951},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.7114645838737488},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6560949087142944},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.6098834276199341},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5883833765983582},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.5812951922416687},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5079246163368225},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.49962902069091797},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.4941895306110382},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4702438414096832},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.4488270580768585},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.22734034061431885},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17932528257369995},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2004.1269098","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269098","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00008049v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00008049","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2004, pp.Vol.2, 1382-3, &#x27E8;10.1109/DATE.2004.1269098&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W4255682579"],"related_works":["https://openalex.org/W4281711577","https://openalex.org/W2178653557","https://openalex.org/W2106200299","https://openalex.org/W2994908368","https://openalex.org/W2502691491","https://openalex.org/W1976012348","https://openalex.org/W2002682434","https://openalex.org/W2137671689","https://openalex.org/W4387782849","https://openalex.org/W2120080222"],"abstract_inverted_index":{"In":[0],"conventional":[1],"multiprocessor":[2],"SoC":[3,55],"(MPSoC)":[4],"design":[5,27,106,110],"methods,":[6],"we":[7,32],"find":[8],"two":[9],"problems:":[10],"lack":[11,17],"of":[12,18,36,45,67,76,92,116,125],"SW":[13,20,84,103],"code":[14],"portability":[15],"and":[16,54,69,104],"early":[19,107],"validation.":[21],"The":[22,41,89],"problems":[23],"cause":[24],"a":[25,34],"long":[26],"cycle.":[28],"To":[29],"resolve":[30],"them,":[31],"present":[33],"concept":[35],"two-layer":[37,78,93],"hardware-dependent":[38],"software":[39],"(HdS).":[40],"presented":[42,77,118],"HdS":[43,79,94],"consists":[44],"hardware":[46],"abstraction":[47,56],"layer":[48,57],"to":[49,58,81,96],"abstract":[50,59],"the":[51,60,65,72,83,98,102,109,114,117,121],"sub-system":[52,70],"architecture":[53,123],"global":[61,68],"MPSoC":[62,122],"architecture.":[63],"During":[64],"exploration":[66,124],"architectures,":[71],"application":[73],"programming":[74],"interfaces":[75],"allow":[80],"keep":[82],"independent":[85],"from":[86],"architectural":[87],"change.":[88],"simulation":[90],"models":[91],"enable":[95],"validate":[97],"entire":[99],"system":[100,129],"including":[101],"HW":[105],"in":[108,120],"steps.":[111],"We":[112],"show":[113],"effectiveness":[115],"methodology":[119],"an":[126],"OpenDiVX":[127],"encoder":[128],"design.":[130]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
