{"id":"https://openalex.org/W4231888422","doi":"https://doi.org/10.1109/date.2004.1269045","title":"An interconnect channel design methodology for high performance integrated circuits","display_name":"An interconnect channel design methodology for high performance integrated circuits","publication_year":2004,"publication_date":"2004-07-20","ids":{"openalex":"https://openalex.org/W4231888422","doi":"https://doi.org/10.1109/date.2004.1269045"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1269045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269045","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016704219","display_name":"Vikas Chandra","orcid":"https://orcid.org/0009-0005-4996-8455"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"V. Chandra","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004513944","display_name":"Anthony Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Xu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078387900","display_name":"Herman Schmit","orcid":"https://orcid.org/0000-0002-0109-7604"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Schmit","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033242808","display_name":"Larry Pileggi","orcid":"https://orcid.org/0000-0002-8605-8240"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. Pileggi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5016704219"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":3.2393,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.92696876,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1138","last_page":"1143"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6438129544258118},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5910680294036865},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.5375485420227051},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5373721122741699},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5240607261657715},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.5160398483276367},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.511597216129303},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.49813246726989746},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42709076404571533},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.41772815585136414},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2334555685520172},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21808108687400818},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2009754478931427},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15169259905815125}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6438129544258118},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5910680294036865},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.5375485420227051},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5373721122741699},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5240607261657715},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.5160398483276367},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.511597216129303},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.49813246726989746},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42709076404571533},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.41772815585136414},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2334555685520172},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21808108687400818},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2009754478931427},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15169259905815125},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1269045","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1269045","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6000000238418579,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1942091197","https://openalex.org/W2005846636","https://openalex.org/W2010008605","https://openalex.org/W2044566319","https://openalex.org/W2056091264","https://openalex.org/W2120062652","https://openalex.org/W2123184444","https://openalex.org/W2126408719","https://openalex.org/W2141242940","https://openalex.org/W2160010046","https://openalex.org/W2160642395","https://openalex.org/W2169049905","https://openalex.org/W2170730458","https://openalex.org/W2171825402","https://openalex.org/W4206218377","https://openalex.org/W4237126129","https://openalex.org/W4240110784","https://openalex.org/W4302593574","https://openalex.org/W6651687513","https://openalex.org/W6678338498","https://openalex.org/W6681115917","https://openalex.org/W6723152695"],"related_works":["https://openalex.org/W2366617252","https://openalex.org/W4389672975","https://openalex.org/W2078506771","https://openalex.org/W2126983197","https://openalex.org/W1965232212","https://openalex.org/W1987513258","https://openalex.org/W2109207559","https://openalex.org/W2146942794","https://openalex.org/W1963851171","https://openalex.org/W2105463171"],"abstract_inverted_index":{"On-chip":[0],"communication":[1,20],"is":[2,110],"becoming":[3],"a":[4,81,111,140],"bottleneck":[5],"for":[6,17,41,155],"high":[7,43],"performance":[8,44],"designs.":[9,50],"Conventional":[10],"interconnect":[11,32,89],"design":[12],"methodology":[13,58,82],"does":[14],"not":[15],"account":[16],"architectures":[18,54],"and/or":[19],"schemes":[21],"that":[22,101],"require":[23,55],"storage":[24],"buffers":[25],"(first-in-first-out":[26],"queues":[27],"or":[28,93],"FIFOs)":[29],"in":[30,66,87,97,107,162],"the":[31,61,64,67,70,85,102,105,108,152,156,160,163],"channel.":[33,164],"For":[34,139],"example,":[35],"FIFOs":[36,65,86,95,106,161],"and":[37,46,121,131],"flow-control":[38],"are":[39],"needed":[40],"Network-on-Chip,":[42],"ASICs":[45],"multiple":[47],"clock":[48,142],"domain":[49],"These":[51],"IC":[52],"implementation":[53],"an":[56,88,147],"efficient":[57,148],"to":[59,83],"determine":[60],"size":[62,84],"of":[63,104,113,127,159],"channel":[68,90,109,128],"since":[69],"FIFO":[71],"sizes":[72],"affect":[73],"system":[74,114],"performance.":[75,138],"In":[76],"this":[77],"work":[78],"we":[79,132,144],"devised":[80],"containing":[91],"one":[92],"more":[94],"connected":[96],"series.":[98],"We":[99],"show":[100],"sizing":[103,158],"function":[112],"parameters":[115],"such":[116],"as":[117],"data":[118,124],"production":[119],"rate":[120],"consumption":[122],"rate,":[123],"burstiness,":[125],"number":[126],"stages":[129],"etc.":[130],"also":[133],"quantify":[134],"their":[135],"effect":[136],"on":[137],"single":[141],"design,":[143],"have":[145],"developed":[146],"algorithm":[149],"which":[150],"reduces":[151],"search":[153],"space":[154],"optimal":[157]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-28T14:05:53.105641","created_date":"2025-10-10T00:00:00"}
