{"id":"https://openalex.org/W4232143692","doi":"https://doi.org/10.1109/date.2004.1268980","title":"Design of sub-10-picoseconds on-chip time measurement circuit","display_name":"Design of sub-10-picoseconds on-chip time measurement circuit","publication_year":2004,"publication_date":"2004-07-20","ids":{"openalex":"https://openalex.org/W4232143692","doi":"https://doi.org/10.1109/date.2004.1268980"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268980","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268980","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028402173","display_name":"M. Amir Abas","orcid":null},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"M.A. Abas","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Newcastle, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083385963","display_name":"G. Russell","orcid":"https://orcid.org/0000-0002-7989-8989"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"G. Russell","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Newcastle, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109215825","display_name":"D.J. Kinniment","orcid":null},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D.J. Kinniment","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Newcastle, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Newcastle, UK","institution_ids":["https://openalex.org/I84884186"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I84884186"],"apc_list":null,"apc_paid":null,"fwci":1.241,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.80801909,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"804","last_page":"809"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6506118774414062},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5716967582702637},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5420255661010742},{"id":"https://openalex.org/keywords/interpolation","display_name":"Interpolation (computer graphics)","score":0.4733315110206604},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4686436355113983},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.44075486063957214},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4218241572380066},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3437492847442627},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2091139554977417},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.1648026704788208},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08686590194702148}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6506118774414062},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5716967582702637},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5420255661010742},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.4733315110206604},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4686436355113983},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44075486063957214},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4218241572380066},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3437492847442627},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2091139554977417},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.1648026704788208},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08686590194702148}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1268980","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268980","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2034517250","https://openalex.org/W2116013847","https://openalex.org/W2128282260","https://openalex.org/W2148172069"],"related_works":["https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2115579119","https://openalex.org/W2136854845","https://openalex.org/W1929041301","https://openalex.org/W2038859986","https://openalex.org/W2104315811","https://openalex.org/W2142217172","https://openalex.org/W4230312832","https://openalex.org/W1982273910"],"abstract_inverted_index":{"The":[0,69],"rapid":[1],"pace":[2],"of":[3,11,25,92,105],"change":[4],"in":[5,9],"IC":[6,18],"technology,":[7],"specifically":[8],"speed":[10,34],"operation,":[12],"demands":[13,30],"sophisticated":[14],"design":[15,79,126],"solutions":[16],"for":[17,31,57,80],"testing":[19,32],"methodologies.":[20],"Moreover,":[21],"the":[22,37],"current":[23],"technology":[24],"system-on-chip":[26],"(SOC)":[27],"makes":[28],"great":[29],"internal":[33,41],"accurately":[35],"as":[36],"limitation":[38],"on":[39],"accessing":[40],"nodes":[42],"using":[43],"I/O":[44],"pins":[45],"becomes":[46],"more":[47],"difficult.":[48],"This":[49],"paper":[50],"presents":[51],"two":[52,70,86,117],"high-resolution":[53],"time":[54,67,82],"measurement":[55,83,94],"schemes":[56,71],"digital":[58],"BIST":[59,81],"applications,":[60],"namely:":[61],"two-delay":[62],"interpolation":[63],"method":[64],"(TDIM)":[65],"and":[66,101],"amplifier.":[68],"are":[72,119],"combined":[73],"to":[74,113],"produce":[75],"a":[76,89,102],"completely":[77],"new":[78],"which":[84,95],"offers":[85],"main":[87],"advantages:":[88],"low":[90],"range":[91],"timing":[93],"has":[96],"never":[97],"been":[98],"achieved":[99],"before,":[100],"small":[103],"size":[104],"layout":[106],"occupying":[107],"0.2":[108],"mm/sup":[109],"2/":[110],"or":[111],"equivalent":[112],"3020":[114],"transistors.":[115],"These":[116],"features":[118],"undoubtedly":[120],"compatible":[121],"with":[122],"present":[123],"high-speed":[124],"SOC":[125],"architectures.":[127]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
