{"id":"https://openalex.org/W4248438810","doi":"https://doi.org/10.1109/date.2004.1268958","title":"A fast algorithm for finding maximal empty rectangles for dynamic FPGA placement","display_name":"A fast algorithm for finding maximal empty rectangles for dynamic FPGA placement","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W4248438810","doi":"https://doi.org/10.1109/date.2004.1268958"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268958","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268958","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081779381","display_name":"M. Handa","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Handa","raw_affiliation_strings":["Department of ECECS, University of Cincinnati, Cincinnati, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECECS, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040975645","display_name":"Ranga Vemuri","orcid":"https://orcid.org/0000-0002-4903-2746"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Vemuri","raw_affiliation_strings":["Department of ECECS, University of Cincinnati, Cincinnati, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECECS, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I63135867"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"744","last_page":"745"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8689013123512268},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6271861791610718},{"id":"https://openalex.org/keywords/row","display_name":"Row","score":0.5750241279602051},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5715454816818237},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.5700202584266663},{"id":"https://openalex.org/keywords/binary-logarithm","display_name":"Binary logarithm","score":0.4311530590057373},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4269234836101532},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4257141351699829},{"id":"https://openalex.org/keywords/data-structure","display_name":"Data structure","score":0.42229151725769043},{"id":"https://openalex.org/keywords/row-and-column-spaces","display_name":"Row and column spaces","score":0.41468703746795654},{"id":"https://openalex.org/keywords/time-complexity","display_name":"Time complexity","score":0.414154052734375},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2727337181568146},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18175867199897766},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.14725181460380554},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07807418704032898}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8689013123512268},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6271861791610718},{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.5750241279602051},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5715454816818237},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.5700202584266663},{"id":"https://openalex.org/C63553672","wikidata":"https://www.wikidata.org/wiki/Q581168","display_name":"Binary logarithm","level":2,"score":0.4311530590057373},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4269234836101532},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4257141351699829},{"id":"https://openalex.org/C162319229","wikidata":"https://www.wikidata.org/wiki/Q175263","display_name":"Data structure","level":2,"score":0.42229151725769043},{"id":"https://openalex.org/C104140500","wikidata":"https://www.wikidata.org/wiki/Q2088159","display_name":"Row and column spaces","level":3,"score":0.41468703746795654},{"id":"https://openalex.org/C311688","wikidata":"https://www.wikidata.org/wiki/Q2393193","display_name":"Time complexity","level":2,"score":0.414154052734375},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2727337181568146},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18175867199897766},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.14725181460380554},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07807418704032898},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1268958","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268958","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1823959354","https://openalex.org/W2029626238","https://openalex.org/W2079543149"],"related_works":["https://openalex.org/W2313440505","https://openalex.org/W3123744736","https://openalex.org/W2137691148","https://openalex.org/W1505848319","https://openalex.org/W4281399881","https://openalex.org/W3166006430","https://openalex.org/W4281971614","https://openalex.org/W2049180840","https://openalex.org/W1992086467","https://openalex.org/W4212780544"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"a":[5,25,38],"fast":[6],"algorithm":[7,69],"for":[8],"finding":[9],"empty":[10,32,42],"area":[11,33],"on":[12,21,91],"the":[13,31,35,46,86,92],"FPGA":[14,47],"surface":[15,48],"with":[16],"some":[17],"rectangular":[18],"tasks":[19],"placed":[20],"it.":[22],"We":[23,44],"use":[24],"staircase":[26],"data":[27],"structure":[28],"to":[29],"report":[30],"in":[34],"form":[36],"of":[37,40,61,67,76,81,89],"list":[39],"maximal":[41],"rectangles.":[43],"model":[45],"using":[49],"an":[50],"innovative":[51],"encoding":[52],"scheme":[53],"that":[54],"improves":[55],"runtime":[56],"and":[57,83],"reduces":[58],"memory":[59],"requirement":[60],"our":[62,68],"algorithm.":[63],"Worst-case":[64],"time":[65],"complexity":[66],"is":[70,74,79,85],"O(xy)":[71],"where":[72],"x":[73],"number":[75,80,88],"columns,":[77],"y":[78],"rows,":[82],"x.y":[84],"total":[87],"cells":[90],"FPGA.":[93]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}