{"id":"https://openalex.org/W4234698167","doi":"https://doi.org/10.1109/date.2004.1268924","title":"Automatic scan insertion and pattern generation for asynchronous circuits","display_name":"Automatic scan insertion and pattern generation for asynchronous circuits","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W4234698167","doi":"https://doi.org/10.1109/date.2004.1268924"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268924","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268924","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039317978","display_name":"Aristides Efthymiou","orcid":"https://orcid.org/0000-0002-2472-982X"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"A. Efthymiou","raw_affiliation_strings":["Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040861479","display_name":"C. Sotiriou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127348","display_name":"FORTH Institute of Electronic Structure and Laser","ror":"https://ror.org/02a3mhk13","country_code":"GR","type":"facility","lineage":["https://openalex.org/I4210127348","https://openalex.org/I8901234"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"C. Sotiriou","raw_affiliation_strings":["Institute of Computer Science, FORTH, Heraklion, Greece"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, FORTH, Heraklion, Greece","institution_ids":["https://openalex.org/I4210127348"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108435403","display_name":"D. Edwards","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D. Edwards","raw_affiliation_strings":["Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5039317978"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":0.5091,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.57984145,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"672","last_page":"673"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8687229156494141},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.835075855255127},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7809619903564453},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6971648931503296},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6488638520240784},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5756329894065857},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5429461002349854},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5324448347091675},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.48350003361701965},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4799361824989319},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.45085543394088745},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42508190870285034},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4245398938655853},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.40650230646133423},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40084511041641235},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3866015076637268},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3489813208580017},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2255898416042328},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12165036797523499},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09932878613471985},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09462609887123108},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.08711129426956177},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.06539914011955261},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.06453657150268555}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8687229156494141},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.835075855255127},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7809619903564453},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6971648931503296},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6488638520240784},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5756329894065857},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5429461002349854},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5324448347091675},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.48350003361701965},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4799361824989319},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.45085543394088745},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42508190870285034},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4245398938655853},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.40650230646133423},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40084511041641235},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3866015076637268},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3489813208580017},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2255898416042328},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12165036797523499},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09932878613471985},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09462609887123108},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.08711129426956177},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.06539914011955261},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.06453657150268555},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/date.2004.1268924","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268924","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/445730f5-b1e4-41a3-ad29-536bd9dc281b","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/445730f5-b1e4-41a3-ad29-536bd9dc281b","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Efthymiou, A, Sotiriou, C & Edwards, D 2004, Automatic scan insertion and pattern generation for asynchronous circuits. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition|Proc. Des. Autom. Test Eur. Conf. Exhib. vol. 1, IEEE Computer Society , pp. 672-673, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, 1/07/04. https://doi.org/10.1109/DATE.2004.1268924","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/445730f5-b1e4-41a3-ad29-536bd9dc281b","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/automatic-scan-insertion-and-pattern-generation-for-asynchronous-circuits(445730f5-b1e4-41a3-ad29-536bd9dc281b).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Efthymiou, A, Sotiriou, C & Edwards, D 2004, Automatic scan insertion and pattern generation for asynchronous circuits. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition|Proc. Des. Autom. Test Eur. Conf. Exhib. vol. 1, IEEE Computer Society , pp. 672-673, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, 1/07/04. https://doi.org/10.1109/DATE.2004.1268924","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1558113545","https://openalex.org/W1590506622","https://openalex.org/W1787074469","https://openalex.org/W4234123702","https://openalex.org/W6633348134","https://openalex.org/W6635527428"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2358223609","https://openalex.org/W2157191248","https://openalex.org/W1589327193","https://openalex.org/W1679970298","https://openalex.org/W2168652618","https://openalex.org/W2127247647","https://openalex.org/W1592424226","https://openalex.org/W2090956884","https://openalex.org/W2166402441"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"3/spl":[3,17,88],"Phi/LSSD,":[4],"a":[5,40,48],"novel,":[6],"easily-automatable":[7],"approach":[8,53,77],"for":[9],"scan":[10,20],"insertion":[11],"and":[12,45],"ATPG":[13,50,90],"of":[14,33,67,75],"asynchronous":[15,34,82],"circuits.":[16],"Phi/LSSD":[18,89],"inserts":[19],"latches":[21],"only":[22],"into":[23],"global":[24],"circuit":[25],"feedback":[26,31],"paths,":[27],"leaving":[28],"the":[29,64],"local":[30],"paths":[32],"state-storing":[35],"gates":[36],"intact.":[37],"By":[38],"employing":[39],"three-phase":[41],"LSSD":[42],"clocking":[43],"scheme":[44],"complemented":[46],"by":[47],"novel":[49],"method,":[51],"our":[52,76,87],"achieves":[54],"industrial":[55],"quality":[56],"testability":[57],"with":[58],"significantly":[59],"less":[60],"area":[61],"overhead":[62],"testing":[63],"same":[65],"number":[66],"faults":[68],"compared":[69],"to":[70],"full-scan":[71],"LSSD.":[72],"The":[73],"effectiveness":[74],"is":[78],"demonstrated":[79],"on":[80],"an":[81],"SOC":[83],"interconnection":[84],"fabric,":[85],"where":[86],"tool":[91],"achieved":[92],"over":[93],"99%":[94],"test":[95],"coverage.":[96]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}