{"id":"https://openalex.org/W4234129059","doi":"https://doi.org/10.1109/date.2004.1268895","title":"A scalable ODC-based algorithm for RTL insertion of gated clocks","display_name":"A scalable ODC-based algorithm for RTL insertion of gated clocks","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W4234129059","doi":"https://doi.org/10.1109/date.2004.1268895"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268895","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268895","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029021627","display_name":"P. Babighian","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"P. Babighian","raw_affiliation_strings":["Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Benini","raw_affiliation_strings":["Universit\u00e0 di Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"Universit\u00e0 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035785471","display_name":"E. Macii","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"E. Macii","raw_affiliation_strings":["Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5029021627"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.5091,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.57757644,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"181","issue":null,"first_page":"500","last_page":"505"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.8437929153442383},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7466521859169006},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6623325347900391},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6545896530151367},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5799697041511536},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4318394660949707},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4252728223800659},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.42329761385917664},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.41094905138015747},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3726574778556824},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36074942350387573},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34976649284362793},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1613287329673767},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0690387487411499},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06815546751022339}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.8437929153442383},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7466521859169006},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6623325347900391},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6545896530151367},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5799697041511536},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4318394660949707},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4252728223800659},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.42329761385917664},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.41094905138015747},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3726574778556824},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36074942350387573},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34976649284362793},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1613287329673767},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0690387487411499},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06815546751022339},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1268895","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268895","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1994298038","https://openalex.org/W1996445094","https://openalex.org/W2000378685","https://openalex.org/W2152938140","https://openalex.org/W2567389468","https://openalex.org/W2615428366","https://openalex.org/W4205649155","https://openalex.org/W4236023225"],"related_works":["https://openalex.org/W2952348651","https://openalex.org/W2375742443","https://openalex.org/W2149381099","https://openalex.org/W4200520489","https://openalex.org/W1483190388","https://openalex.org/W2061536531","https://openalex.org/W193873054","https://openalex.org/W2800543810","https://openalex.org/W2132453911","https://openalex.org/W2082756771"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,61],"new":[4],"automatic":[5],"clock-gating":[6],"extraction":[7],"working":[8],"at":[9],"the":[10,68],"RT-level.":[11],"The":[12],"key":[13],"features":[14],"of":[15,41,63,73],"our":[16,74],"approach":[17],"are:":[18],"(i)":[19],"seamless":[20],"merging":[21],"with":[22,35,43],"existing":[23],"industrial":[24,64],"design":[25],"flows":[26],"and":[27,51,56,70],"commercial":[28,47],"tools;":[29,48],"(ii)":[30],"high":[31],"scalability":[32],"to":[33,45],"deal":[34],"large":[36],"circuits;":[37],"(iii)":[38],"improved":[39],"quality":[40],"results":[42],"respect":[44],"available":[46],"(iv)":[49],"smaller":[50],"well-controlled":[52],"overhead":[53],"in":[54],"speed":[55],"area.":[57],"Experimental":[58],"results,":[59],"on":[60],"set":[62],"RTL":[65],"designs,":[66],"demonstrate":[67],"viability":[69],"practical":[71],"impact":[72],"approach.":[75]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}