{"id":"https://openalex.org/W4230342499","doi":"https://doi.org/10.1109/date.2004.1268892","title":"A configurable logic architecture for dynamic hardware/software partitioning","display_name":"A configurable logic architecture for dynamic hardware/software partitioning","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W4230342499","doi":"https://doi.org/10.1109/date.2004.1268892"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268892","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268892","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015269679","display_name":"Roman Lysecky","orcid":"https://orcid.org/0000-0002-5000-0848"},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"R. Lysecky","raw_affiliation_strings":["Department of Computer Science and Engineering, University of California, Riverside, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of California, Riverside, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001290812","display_name":"Frank Vahid","orcid":"https://orcid.org/0000-0001-5416-0032"},"institutions":[{"id":"https://openalex.org/I4210140791","display_name":"Irvine University","ror":"https://ror.org/04ysmca02","country_code":"US","type":"education","lineage":["https://openalex.org/I4210140791"]},{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]},{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. Vahid","raw_affiliation_strings":["Department of Computer Science and Engineering, Center for Embedded Computer Systems at UC Irvine, University of California, Riverside, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Center for Embedded Computer Systems at UC Irvine, University of California, Riverside, USA","institution_ids":["https://openalex.org/I204250578","https://openalex.org/I103635307","https://openalex.org/I4210140791"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5015269679"],"corresponding_institution_ids":["https://openalex.org/I103635307"],"apc_list":null,"apc_paid":null,"fwci":3.309,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":{"value":0.92412231,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"480","last_page":"485"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8107401132583618},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.5741478204727173},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.5516112446784973},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.532069206237793},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5117015838623047},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4721638858318329},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.46301528811454773},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4302857518196106},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.41105708479881287},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3824373781681061},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3447027802467346},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3092137575149536}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8107401132583618},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.5741478204727173},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.5516112446784973},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.532069206237793},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5117015838623047},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4721638858318329},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.46301528811454773},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4302857518196106},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.41105708479881287},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3824373781681061},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3447027802467346},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3092137575149536},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1268892","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268892","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8600000143051147}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1551995088","https://openalex.org/W1583432580","https://openalex.org/W1649101858","https://openalex.org/W2004068104","https://openalex.org/W2006428566","https://openalex.org/W2032094184","https://openalex.org/W2080241541","https://openalex.org/W2109706810","https://openalex.org/W2113764809","https://openalex.org/W2138946897","https://openalex.org/W2142490124","https://openalex.org/W2151970267","https://openalex.org/W2163599210","https://openalex.org/W2169601811","https://openalex.org/W4206627859","https://openalex.org/W4230112597","https://openalex.org/W4231002400","https://openalex.org/W4239035539","https://openalex.org/W4240382364","https://openalex.org/W4248088771","https://openalex.org/W4251880635","https://openalex.org/W6633000043"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2291943064","https://openalex.org/W2209727271","https://openalex.org/W2027176516","https://openalex.org/W1040574563","https://openalex.org/W2281932057"],"abstract_inverted_index":{"In":[0,70],"previous":[1],"work,":[2],"we":[3,38,107,135,169,172],"showed":[4],"the":[5,50,114,122,128],"benefits":[6],"and":[7,46,76,83,139,153,178,183,189,205,224,232],"feasibility":[8],"of":[9,55,116,132],"having":[10],"a":[11,29,85,93,213],"processor":[12],"dynamically":[13],"partition":[14],"its":[15],"executing":[16],"software":[17,21,117],"such":[18,56],"that":[19,109,171,218],"critical":[20],"kernels":[22],"are":[23,200],"transparently":[24],"partitioned":[25],"to":[26,78,164,191,202],"execute":[27,79],"as":[28,179,181],"hardware":[30],"coprocessor":[31],"on":[32,66,84,113,127,176,187],"configurable":[33,43,94,166,209,236],"logic":[34,44,95,210,237],"-":[35],"an":[36],"approach":[37],"call":[39],"warp":[40],"processing.":[41],"The":[42],"place":[45,75,138],"route":[47,77,140],"step":[48],"is":[49],"most":[51],"computationally":[52],"intensive":[53],"part":[54],"hardware/software":[57,100,222,230],"partitioning,":[58,223,231],"normally":[59],"running":[60],"for":[61,98,141,216,229,234],"many":[62],"minutes":[63],"or":[64],"hours":[65],"powerful":[67],"desktop":[68,227],"processors.":[69],"contrast,":[71],"dynamic":[72,99,221],"partitioning":[73,194],"requires":[74],"in":[80,239],"just":[81,196],"seconds":[82],"lean":[86],"embedded":[87],"processor.":[88],"We":[89],"have":[90],"therefore":[91],"designed":[92],"architecture":[96,143,211],"specifically":[97,111],"partitioning.":[101],"Through":[102],"experiments":[103],"with":[104],"popular":[105,160],"benchmarks,":[106],"show":[108,170],"by":[110],"focusing":[112],"goal":[115,131],"kernel":[118],"speedup":[119],"when":[120,193],"designing":[121],"FPGA":[123],"architecture,":[124],"rather":[125],"than":[126,159],"more":[129],"general":[130],"ASIC":[133],"prototyping,":[134],"can":[136],"perform":[137],"our":[142,208],"50":[144],"times":[145,149,155],"faster,":[146],"using":[147],"10,000":[148],"less":[150,156],"data":[151],"memory,":[152,158],"1,000":[154],"code":[157],"commercial":[161,165,203],"tools":[162,204,228],"mapping":[163],"logic.":[167],"Yet,":[168],"obtain":[173],"speedups":[174],"(2x":[175],"average,":[177,188],"much":[180],"4x)":[182],"energy":[184],"savings":[185],"(33%":[186],"up":[190],"74%)":[192],"even":[195,233],"one":[197],"loop,":[198],"which":[199],"comparable":[201],"fabrics.":[206],"Thus,":[207],"represents":[212],"good":[214],"candidate":[215],"platforms":[217],"will":[219],"support":[220],"enables":[225],"ultra-fast":[226],"fast":[235],"design":[238],"general.":[240]},"counts_by_year":[{"year":2020,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
