{"id":"https://openalex.org/W3136117375","doi":"https://doi.org/10.1109/date.2004.1268881","title":"Synchro-tokens: eliminating nondeterminism to enable chip-level test of globally-asynchronous SoC's","display_name":"Synchro-tokens: eliminating nondeterminism to enable chip-level test of globally-asynchronous SoC's","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W3136117375","doi":"https://doi.org/10.1109/date.2004.1268881","mag":"3136117375"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268881","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074730199","display_name":"M.W. Heath","orcid":null},"institutions":[{"id":"https://openalex.org/I24603500","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521","country_code":"US","type":"education","lineage":["https://openalex.org/I24603500"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.W. Heath","raw_affiliation_strings":["University of Massachusetts, Amherst, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Massachusetts, Amherst, USA","institution_ids":["https://openalex.org/I24603500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033415719","display_name":"Wayne Burleson","orcid":"https://orcid.org/0000-0002-7068-4351"},"institutions":[{"id":"https://openalex.org/I24603500","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521","country_code":"US","type":"education","lineage":["https://openalex.org/I24603500"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.P. Burleson","raw_affiliation_strings":["University of Massachusetts, Amherst, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Massachusetts, Amherst, USA","institution_ids":["https://openalex.org/I24603500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037855756","display_name":"Ian G. Harris","orcid":"https://orcid.org/0000-0003-3244-6528"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"I.G. Harris","raw_affiliation_strings":["University of California, Irvine, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"410","last_page":"415"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7970287799835205},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6637365818023682},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6158062815666199},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.5405181646347046},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.5135750770568848},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.49730709195137024},{"id":"https://openalex.org/keywords/nondeterministic-algorithm","display_name":"Nondeterministic algorithm","score":0.4571497440338135},{"id":"https://openalex.org/keywords/logic-analyzer","display_name":"Logic analyzer","score":0.4512440860271454},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.4452449679374695},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39193105697631836},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.2322283685207367},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11111554503440857},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.0980503261089325}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7970287799835205},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6637365818023682},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6158062815666199},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.5405181646347046},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.5135750770568848},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.49730709195137024},{"id":"https://openalex.org/C176181172","wikidata":"https://www.wikidata.org/wiki/Q3490301","display_name":"Nondeterministic algorithm","level":2,"score":0.4571497440338135},{"id":"https://openalex.org/C188434589","wikidata":"https://www.wikidata.org/wiki/Q1478762","display_name":"Logic analyzer","level":3,"score":0.4512440860271454},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.4452449679374695},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39193105697631836},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2322283685207367},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11111554503440857},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.0980503261089325},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C158007255","wikidata":"https://www.wikidata.org/wiki/Q1055222","display_name":"Spectrum analyzer","level":2,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2004.1268881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268881","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},{"id":"pmh:oai:scholarworks.umass.edu:20.500.14394/20931","is_oa":false,"landing_page_url":"https://hdl.handle.net/20.500.14394/20931","pdf_url":null,"source":{"id":"https://openalex.org/S4306402057","display_name":"Scholarworks (University of Massachusetts Amherst)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I24603500","host_organization_name":"University of Massachusetts Amherst","host_organization_lineage":["https://openalex.org/I24603500"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"published","raw_type":"article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4000000059604645,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1609287256","https://openalex.org/W1834098275","https://openalex.org/W1867214288","https://openalex.org/W2033045135","https://openalex.org/W2085950572","https://openalex.org/W2113486165","https://openalex.org/W2117897741","https://openalex.org/W2125394330","https://openalex.org/W2129900191","https://openalex.org/W2134157563","https://openalex.org/W2144225549","https://openalex.org/W2145314233","https://openalex.org/W2154636015","https://openalex.org/W2165642910","https://openalex.org/W2168916081","https://openalex.org/W2503952136","https://openalex.org/W4234807381","https://openalex.org/W6676717505"],"related_works":["https://openalex.org/W2380488590","https://openalex.org/W2381770863","https://openalex.org/W1989099935","https://openalex.org/W2387092654","https://openalex.org/W1543057232","https://openalex.org/W3164310312","https://openalex.org/W2361961910","https://openalex.org/W4250908141","https://openalex.org/W3021097839","https://openalex.org/W2008760841"],"abstract_inverted_index":{"Globally":[0],"asynchronous":[1,34],"locally":[2,28],"synchronous":[3,21,105],"(GALS)":[4],"clocking":[5],"applied":[6],"to":[7,94],"a":[8,13,20,27,72,81,98],"system-on-a-chip":[9],"(SoC)":[10],"results":[11],"in":[12,15],"design":[14],"which":[16,67],"each":[17],"core":[18],"is":[19,33],"block":[22],"(SB)":[23],"of":[24,76,101,117,120,125],"logic":[25,39],"with":[26],"generated":[29],"clock.":[30],"Inter-core":[31],"communication":[32],"and":[35,55,59,107,113,123],"controlled":[36],"by":[37,47],"wrapper":[38],"around":[40],"the":[41],"cores.":[42],"The":[43,115],"nondeterministic":[44],"synchronization":[45],"used":[46],"most":[48],"GALS":[49,62,84],"architectures":[50],"makes":[51],"chip-level":[52],"silicon":[53],"debug":[54,106],"functional":[56],"test":[57,108],"difficult":[58],"costly.":[60],"Deterministic":[61],"methodologies":[63,109],"make":[64],"dataflow":[65],"assumptions":[66],"are":[68,91,128],"only":[69],"valid":[70],"for":[71,97],"very":[73],"limited":[74],"set":[75],"applications.":[77],"This":[78],"paper":[79],"describes":[80],"novel":[82],"deterministic":[83],"methodology":[85],"called":[86],"\"synchro-tokens\"":[87],"whose":[88],"parameterized":[89],"wrappers":[90],"flexible":[92],"enough":[93],"be":[95],"useful":[96],"wide":[99],"range":[100],"applications":[102],"while":[103],"supporting":[104],"such":[110],"as":[111],"1149.1":[112],"P1500.":[114],"validation":[116],"determinism,":[118],"estimation":[119],"area":[121],"overhead,":[122],"analysis":[124],"performance":[126],"impact":[127],"detailed.":[129]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}