{"id":"https://openalex.org/W4249564707","doi":"https://doi.org/10.1109/date.2004.1268880","title":"Scan power minimization through stimulus and response transformations","display_name":"Scan power minimization through stimulus and response transformations","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W4249564707","doi":"https://doi.org/10.1109/date.2004.1268880"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268880","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268880","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059987567","display_name":"Ozgur Sinanoglu","orcid":"https://orcid.org/0000-0003-0782-0397"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"O. Sinanoglu","raw_affiliation_strings":["Computer Science and Engineering Department, University of California, San Diego, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering Department, University of California, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043071397","display_name":"A. Orailoglu","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Orailoglu","raw_affiliation_strings":["Computer Science and Engineering Department, University of California, San Diego, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering Department, University of California, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5059987567"],"corresponding_institution_ids":["https://openalex.org/I36258959"],"apc_list":null,"apc_paid":null,"fwci":2.5453,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.8788222,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"19","issue":null,"first_page":"404","last_page":"409"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.6400039196014404},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6159456968307495},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5561314821243286},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5496474504470825},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5141008496284485},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5086954236030579},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.460472971200943},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.44943323731422424},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43685102462768555},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4130842685699463},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4119296073913574},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4022407829761505},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2587413489818573},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.24755358695983887},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.1854279339313507},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17297011613845825},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.15021643042564392},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08872488141059875}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.6400039196014404},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6159456968307495},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5561314821243286},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5496474504470825},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5141008496284485},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5086954236030579},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.460472971200943},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.44943323731422424},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43685102462768555},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4130842685699463},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4119296073913574},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4022407829761505},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2587413489818573},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.24755358695983887},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.1854279339313507},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17297011613845825},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.15021643042564392},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08872488141059875},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1268880","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268880","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1557475698","https://openalex.org/W1660272255","https://openalex.org/W2079150276","https://openalex.org/W2080510479","https://openalex.org/W2102168889","https://openalex.org/W2106303764","https://openalex.org/W2126641963","https://openalex.org/W2130439920","https://openalex.org/W2135622428","https://openalex.org/W2139356796","https://openalex.org/W2148192475","https://openalex.org/W2150860197","https://openalex.org/W2169839635","https://openalex.org/W6636974747"],"related_works":["https://openalex.org/W2143881398","https://openalex.org/W2118952760","https://openalex.org/W2075356617","https://openalex.org/W2274367941","https://openalex.org/W2390529848","https://openalex.org/W2763030692","https://openalex.org/W2092894550","https://openalex.org/W1974621628","https://openalex.org/W3088373974","https://openalex.org/W2789575913"],"abstract_inverted_index":{"Scan-based":[0],"cores":[1,45,52],"impose":[2],"considerable":[3],"test":[4,17,41,62,86,102,123,150,153],"power":[5,18,31,42],"challenges":[6],"due":[7],"to":[8,23,91],"excessive":[9],"switching":[10],"activity":[11],"during":[12,97],"shift":[13,98],"cycles.":[14],"The":[15,83,152],"consequent":[16,84],"constraints":[19],"force":[20],"SOC":[21,44,61],"designers":[22],"sacrifice":[24],"parallelism":[25],"among":[26],"core":[27],"tests,":[28],"as":[29,137,186],"exceeding":[30],"thresholds":[32],"may":[33],"damage":[34],"the":[35,49,80,93,112,122,134,139,148,164,180,183],"chip":[36],"being":[37],"tested.":[38],"Reduction":[39],"of":[40,51,114,145,182],"for":[43],"can":[46,54],"thus":[47],"increase":[48],"number":[50],"that":[53,75,110],"be":[55],"tested":[56],"in":[57,159],"parallel,":[58],"improving":[59],"significantly":[60],"application":[63],"time.":[64],"In":[65],"this":[66],"paper,":[67],"we":[68,130,141],"propose":[69,142],"a":[70,106],"scan":[71,81,94,119,167],"chain":[72,95,168],"modification":[73],"technique":[74],"inserts":[76],"logic":[77,115],"gates":[78],"on":[79,121],"path.":[82],"beneficial":[85],"data":[87],"transformations":[88,127,136],"are":[89,157],"utilized":[90],"reduce":[92],"transitions":[96],"cycles":[99],"and":[100,125,155],"hence":[101],"power.":[103,151],"We":[104],"introduce":[105],"matrix":[107],"band":[108],"algebra":[109],"models":[111],"impact":[113],"gate":[116],"insertion":[117],"between":[118],"cells":[120],"stimulus":[124],"response":[126,135],"realized.":[128],"As":[129],"have":[131],"successfully":[132],"modeled":[133],"well,":[138],"methodology":[140,185],"is":[143,171],"capable":[144],"truly":[146],"minimizing":[147],"overall":[149],"vectors":[154],"responses":[156],"analyzed":[158],"an":[160],"intertwined":[161],"manner,":[162],"identifying":[163],"best":[165],"possible":[166],"modification,":[169],"which":[170],"realized":[172],"at":[173],"minimal":[174],"area":[175],"cost.":[176],"Experimental":[177],"results":[178],"justify":[179],"efficacy":[181],"proposed":[184],"well.":[187]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}