{"id":"https://openalex.org/W4233035613","doi":"https://doi.org/10.1109/date.2004.1268841","title":"Scheduling reusable instructions for power reduction","display_name":"Scheduling reusable instructions for power reduction","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W4233035613","doi":"https://doi.org/10.1109/date.2004.1268841"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268841","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081746360","display_name":"J.S. Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.S. Hu","raw_affiliation_strings":["Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045197454","display_name":"N. Vijaykrishnan","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Vijaykrishnan","raw_affiliation_strings":["Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111262396","display_name":"Seungsu Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Kim","raw_affiliation_strings":["Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049326265","display_name":"M. Kandemir","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Kandemir","raw_affiliation_strings":["Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066703370","display_name":"M.J. Irwin","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.J. Irwin","raw_affiliation_strings":["Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Microsystems Design Laboratory, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130769515"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"148","last_page":"153 Vol.1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8751682043075562},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.6515883207321167},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6233314275741577},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6171377301216125},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.6042349338531494},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.5761922001838684},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5598003268241882},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.4532897472381592},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4455149173736572},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.437412291765213},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4314248859882355},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.42647624015808105},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37195008993148804},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.34192705154418945},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.2516877353191376},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.2165561318397522},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1739475429058075},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.13016605377197266}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8751682043075562},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.6515883207321167},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6233314275741577},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6171377301216125},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.6042349338531494},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.5761922001838684},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5598003268241882},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.4532897472381592},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4455149173736572},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.437412291765213},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4314248859882355},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.42647624015808105},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37195008993148804},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34192705154418945},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.2516877353191376},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.2165561318397522},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1739475429058075},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.13016605377197266},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1268841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268841","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8299999833106995,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W2047021623","https://openalex.org/W2112833506","https://openalex.org/W2120636791","https://openalex.org/W2129254788","https://openalex.org/W2134872659","https://openalex.org/W2148858136","https://openalex.org/W3140903683","https://openalex.org/W4230345175","https://openalex.org/W4231070018","https://openalex.org/W4241752870","https://openalex.org/W4254288653","https://openalex.org/W6602613798","https://openalex.org/W6676725599","https://openalex.org/W6792941224"],"related_works":["https://openalex.org/W2557008360","https://openalex.org/W1989320170","https://openalex.org/W2493736956","https://openalex.org/W3198202560","https://openalex.org/W2062603907","https://openalex.org/W2000718530","https://openalex.org/W1997758669","https://openalex.org/W4243004653","https://openalex.org/W4239584669","https://openalex.org/W2080993955"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"a":[5,87,109],"new":[6],"issue":[7,19,37,105],"queue":[8,20,38],"design":[9],"that":[10,71,119],"is":[11,21,28],"capable":[12],"of":[13,54,58,75,90,115],"scheduling":[14],"reusable":[15],"instructions.":[16],"Once":[17],"the":[18,31,36,52,55,59,76,80,93,98,104,120],"reusing":[22],"instructions,":[23],"no":[24],"instruction":[25,45,94],"cache":[26],"access":[27],"needed":[29],"since":[30],"instructions":[32],"are":[33],"supplied":[34],"by":[35,127],"itself.":[39],"Furthermore,":[40],"dynamic":[41],"branch":[42,99],"prediction":[43],"and":[44,101],"decoding":[46],"can":[47,83,123],"also":[48],"be":[49,84,124],"avoided":[50],"permitting":[51],"gating":[53],"front-end":[56,82],"stages":[57,62],"pipeline":[60,81],"(the":[61],"before":[63],"register":[64],"renaming).":[65],"Results":[66],"using":[67,128],"array-intensive":[68],"codes":[69],"show":[70],"up":[72],"to":[73],"82%":[74],"total":[77],"execution":[78],"cycles,":[79],"gated,":[85],"providing":[86],"power":[88,121],"reduction":[89],"72%":[91],"in":[92,97,103],"cache,":[95],"33%":[96],"predictor,":[100],"21%":[102],"queue,":[106],"respectively,":[107],"at":[108],"small":[110],"performance":[111],"cost.":[112],"Our":[113],"analysis":[114],"compiler":[116],"optimizations":[117],"indicates":[118],"savings":[122],"further":[125],"improved":[126],"optimized":[129],"code.":[130]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
