{"id":"https://openalex.org/W4239326162","doi":"https://doi.org/10.1109/date.2004.1268836","title":"Loop shifting and compaction for the high-level synthesis of designs with complex control flow","display_name":"Loop shifting and compaction for the high-level synthesis of designs with complex control flow","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W4239326162","doi":"https://doi.org/10.1109/date.2004.1268836"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268836","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268836","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038382467","display_name":"Sumit Kumar Gupta","orcid":"https://orcid.org/0000-0003-2292-950X"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Gupta","raw_affiliation_strings":["Center for Embedded Computer Systems, School of Information and Computer Science, University of California, Irvine, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, School of Information and Computer Science, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007817952","display_name":"Nikil Dutt","orcid":"https://orcid.org/0000-0002-3060-8119"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Dutt","raw_affiliation_strings":["Center for Embedded Computer Systems, School of Information and Computer Science, University of California, Irvine, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, School of Information and Computer Science, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078959213","display_name":"Rajesh K. Gupta","orcid":"https://orcid.org/0000-0002-6489-7633"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Gupta","raw_affiliation_strings":["Center for Embedded Computer Systems, Department of Computer Science and Engineering, University of California, San Diego, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, Department of Computer Science and Engineering, University of California, San Diego, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102973689","display_name":"A. Nicolau","orcid":"https://orcid.org/0000-0003-0198-2475"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Nicolau","raw_affiliation_strings":["Center for Embedded Computer Systems, School of Information and Computer Science, University of California, Irvine, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, School of Information and Computer Science, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"114","last_page":"119"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7575840950012207},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.7570828199386597},{"id":"https://openalex.org/keywords/nested-loop-join","display_name":"Nested loop join","score":0.7474289536476135},{"id":"https://openalex.org/keywords/loop-fission","display_name":"Loop fission","score":0.7418975830078125},{"id":"https://openalex.org/keywords/loop-tiling","display_name":"Loop tiling","score":0.6488045454025269},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.585196316242218},{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"Loop unrolling","score":0.5634387135505676},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.5500914454460144},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5217945575714111},{"id":"https://openalex.org/keywords/loop-fusion","display_name":"Loop fusion","score":0.5167871713638306},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5115333795547485},{"id":"https://openalex.org/keywords/flow-control","display_name":"Flow control (data)","score":0.48752734065055847},{"id":"https://openalex.org/keywords/feedback-loop","display_name":"Feedback loop","score":0.4333485960960388},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.42069464921951294},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.32193946838378906},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2217780351638794},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22044602036476135},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.2017863392829895},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08291393518447876}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7575840950012207},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.7570828199386597},{"id":"https://openalex.org/C1306188","wikidata":"https://www.wikidata.org/wiki/Q4060687","display_name":"Nested loop join","level":2,"score":0.7474289536476135},{"id":"https://openalex.org/C134718785","wikidata":"https://www.wikidata.org/wiki/Q6675821","display_name":"Loop fission","level":3,"score":0.7418975830078125},{"id":"https://openalex.org/C11799548","wikidata":"https://www.wikidata.org/wiki/Q6675847","display_name":"Loop tiling","level":3,"score":0.6488045454025269},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.585196316242218},{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.5634387135505676},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.5500914454460144},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5217945575714111},{"id":"https://openalex.org/C82653869","wikidata":"https://www.wikidata.org/wiki/Q6675821","display_name":"Loop fusion","level":3,"score":0.5167871713638306},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5115333795547485},{"id":"https://openalex.org/C186766456","wikidata":"https://www.wikidata.org/wiki/Q612457","display_name":"Flow control (data)","level":2,"score":0.48752734065055847},{"id":"https://openalex.org/C186886427","wikidata":"https://www.wikidata.org/wiki/Q5441213","display_name":"Feedback loop","level":2,"score":0.4333485960960388},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.42069464921951294},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.32193946838378906},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2217780351638794},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22044602036476135},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.2017863392829895},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08291393518447876},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1268836","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268836","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.4099999964237213,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1816081266","https://openalex.org/W1838978217","https://openalex.org/W1976339994","https://openalex.org/W2033710438","https://openalex.org/W2054652902","https://openalex.org/W2103581911","https://openalex.org/W2129926024","https://openalex.org/W2139842982","https://openalex.org/W2142899035","https://openalex.org/W2156678313","https://openalex.org/W2168460756","https://openalex.org/W4230232370","https://openalex.org/W4232919122","https://openalex.org/W4237320801","https://openalex.org/W4244015025","https://openalex.org/W4252402022","https://openalex.org/W6638474818","https://openalex.org/W6681361974","https://openalex.org/W6684880667"],"related_works":["https://openalex.org/W2342605656","https://openalex.org/W2040522199","https://openalex.org/W2340721088","https://openalex.org/W4251798485","https://openalex.org/W2122418911","https://openalex.org/W1543710109","https://openalex.org/W2119560736","https://openalex.org/W1993227264","https://openalex.org/W2017719803","https://openalex.org/W2727330431"],"abstract_inverted_index":{"Emerging":[0],"embedded":[1],"system":[2],"applications":[3],"in":[4,94,99,116,120],"multimedia":[5,144],"and":[6,20,39,102,135,145],"image":[7,146],"processing":[8,147],"are":[9],"characterized":[10],"by":[11,37],"complex":[12,61],"control":[13,62],"flow":[14],"consisting":[15],"of":[16,58,85],"deeply":[17],"nested":[18],"conditionals":[19],"loops.":[21],"We":[22,124],"present":[23,136],"a":[24,91],"technique":[25],"called":[26],"loop":[27,32,43,50,79,87,106,126],"shifting":[28,38,51,107,127],"that":[29,49],"incrementally":[30],"exploits":[31],"level":[33],"parallelism":[34],"across":[35,42],"iterations":[36],"compacting":[40],"operations":[41],"iterations.":[44],"Our":[45],"experimental":[46],"results":[47,137],"show":[48],"is":[52,67,108],"particularly":[53],"effective":[54],"for":[55,138],"the":[56,86,95,100,103,117,121,129],"synthesis":[57,133],"designs":[59,141],"with":[60],"especially":[63],"when":[64,77],"resource":[65,73],"utilization":[66],"already":[68],"high":[69],"and/or":[70],"under":[71],"tight":[72],"constraints.":[74],"In":[75],"situations":[76],"further":[78],"unrolling":[80],"(or":[81],"initiating":[82],"another":[83],"iteration":[84],"body)":[88],"leads":[89],"to":[90,110,113],"sharp":[92],"increase":[93],"longest":[96],"combinational":[97],"path":[98],"circuit":[101,104],"area,":[105],"able":[109],"achieve":[111],"up":[112],"20%":[114],"reduction":[115],"input-to-output":[118],"delay":[119],"synthesized":[122],"circuit.":[123],"implemented":[125],"within":[128],"SPARK":[130],"parallelizing":[131],"high-level":[132],"framework":[134],"experiments":[139],"on":[140],"derived":[142],"from":[143],"applications.":[148]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
