{"id":"https://openalex.org/W4256084152","doi":"https://doi.org/10.1109/date.2004.1268835","title":"Layout conscious bus architecture synthesis for deep submicron systems on chip","display_name":"Layout conscious bus architecture synthesis for deep submicron systems on chip","publication_year":2004,"publication_date":"2004-06-21","ids":{"openalex":"https://openalex.org/W4256084152","doi":"https://doi.org/10.1109/date.2004.1268835"},"language":"en","primary_location":{"id":"doi:10.1109/date.2004.1268835","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268835","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073213552","display_name":"N. Thepayasuwan","orcid":null},"institutions":[{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]},{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"N. Thepayasuwan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, State University of New York, Stony Brook, Stony Brook, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State University of New York, Stony Brook, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I59553526","https://openalex.org/I1327163397"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080972445","display_name":"Alex Doboli","orcid":"https://orcid.org/0000-0003-2472-4014"},"institutions":[{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]},{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Doboli","raw_affiliation_strings":["Department of Electrical and Computer Engineering, State University of New York, Stony Brook, Stony Brook, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State University of New York, Stony Brook, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I59553526","https://openalex.org/I1327163397"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5073213552"],"corresponding_institution_ids":["https://openalex.org/I1327163397","https://openalex.org/I59553526"],"apc_list":null,"apc_paid":null,"fwci":2.7999,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.89694224,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"108","last_page":"113"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7031379342079163},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6283497214317322},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5798372626304626},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5635024905204773},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5540527105331421},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.5369178652763367},{"id":"https://openalex.org/keywords/bus-network","display_name":"Bus network","score":0.515224277973175},{"id":"https://openalex.org/keywords/local-bus","display_name":"Local bus","score":0.4728681743144989},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4550723135471344},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45357123017311096},{"id":"https://openalex.org/keywords/communications-system","display_name":"Communications system","score":0.4300050139427185},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4268518388271332},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.34100276231765747},{"id":"https://openalex.org/keywords/control-bus","display_name":"Control bus","score":0.31164348125457764},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3013833463191986},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.19306045770645142}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7031379342079163},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6283497214317322},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5798372626304626},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5635024905204773},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5540527105331421},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.5369178652763367},{"id":"https://openalex.org/C54609922","wikidata":"https://www.wikidata.org/wiki/Q748329","display_name":"Bus network","level":4,"score":0.515224277973175},{"id":"https://openalex.org/C202015219","wikidata":"https://www.wikidata.org/wiki/Q6664300","display_name":"Local bus","level":4,"score":0.4728681743144989},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4550723135471344},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45357123017311096},{"id":"https://openalex.org/C101765175","wikidata":"https://www.wikidata.org/wiki/Q577764","display_name":"Communications system","level":2,"score":0.4300050139427185},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4268518388271332},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.34100276231765747},{"id":"https://openalex.org/C203315745","wikidata":"https://www.wikidata.org/wiki/Q2235486","display_name":"Control bus","level":3,"score":0.31164348125457764},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3013833463191986},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.19306045770645142},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2004.1268835","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2004.1268835","pdf_url":null,"source":{"id":"https://openalex.org/S4363608792","display_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1987786682","https://openalex.org/W2079144805","https://openalex.org/W2126413277","https://openalex.org/W2137185684","https://openalex.org/W2165437459","https://openalex.org/W2185754723","https://openalex.org/W4243733055","https://openalex.org/W4249224491","https://openalex.org/W4253641002","https://openalex.org/W6814683480"],"related_works":["https://openalex.org/W2387146226","https://openalex.org/W4255235451","https://openalex.org/W70103254","https://openalex.org/W51382759","https://openalex.org/W2404980846","https://openalex.org/W2362390174","https://openalex.org/W2352926601","https://openalex.org/W2388085031","https://openalex.org/W2614336368","https://openalex.org/W4244800129"],"abstract_inverted_index":{"System-level":[0],"design":[1],"has":[2],"a":[3,35,83,87],"disadvantage":[4],"in":[5,21],"not":[6],"knowing":[7],"important":[8],"aspects":[9],"about":[10],"the":[11,44,72,78],"final":[12],"layout.":[13],"This":[14,32],"is":[15],"critical":[16],"for":[17,42,82],"SoC,":[18],"where":[19],"uncertainties":[20],"communication":[22,45],"delay":[23],"by":[24],"very":[25],"deep":[26],"submicron":[27],"effects":[28],"cannot":[29],"be":[30],"neglected.":[31],"paper":[33,76],"presents":[34,77],"layout-aware":[36],"bus":[37,54,65],"architecture":[38],"(BA)":[39],"synthesis":[40,51],"algorithm":[41],"designing":[43],"sub-system":[46],"of":[47],"an":[48],"SoC.":[49,89],"BA":[50,79],"includes":[52],"finding":[53],"topology":[55],"and":[56,67,86],"routing":[57],"individual":[58],"buses,":[59],"so":[60],"that":[61],"constraints":[62],"like":[63],"area,":[64],"speed":[66],"length,":[68],"are":[69],"tackled":[70],"at":[71],"physical":[73],"level.":[74],"The":[75],"automatically":[80],"synthesized":[81],"network":[84],"processor":[85],"JPEG":[88]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
