{"id":"https://openalex.org/W4247001691","doi":"https://doi.org/10.1109/date.2003.1253665","title":"Enhancing signal integrity through a low-overhead encoding scheme on address buses","display_name":"Enhancing signal integrity through a low-overhead encoding scheme on address buses","publication_year":2003,"publication_date":"2003-12-22","ids":{"openalex":"https://openalex.org/W4247001691","doi":"https://doi.org/10.1109/date.2003.1253665"},"language":"en","primary_location":{"id":"doi:10.1109/date.2003.1253665","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2003.1253665","pdf_url":null,"source":{"id":"https://openalex.org/S4363607952","display_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047096819","display_name":"T. Lv","orcid":"https://orcid.org/0009-0009-6487-7796"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Lv","raw_affiliation_strings":["Princeton University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063508488","display_name":"J\u00f6rg Henkel","orcid":"https://orcid.org/0000-0001-9602-2922"},"institutions":[{"id":"https://openalex.org/I4210107353","display_name":"NEC (United States)","ror":"https://ror.org/01v791m31","country_code":"US","type":"company","lineage":["https://openalex.org/I118347220","https://openalex.org/I4210107353"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Henkel","raw_affiliation_strings":["NEC Corporation Limited, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NEC Corporation Limited, USA","institution_ids":["https://openalex.org/I4210107353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034045111","display_name":"Haris Lekatsas","orcid":null},"institutions":[{"id":"https://openalex.org/I4210107353","display_name":"NEC (United States)","ror":"https://ror.org/01v791m31","country_code":"US","type":"company","lineage":["https://openalex.org/I118347220","https://openalex.org/I4210107353"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Lekatsas","raw_affiliation_strings":["NEC Corporation Limited, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NEC Corporation Limited, USA","institution_ids":["https://openalex.org/I4210107353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004682100","display_name":"Marilyn Wolf","orcid":"https://orcid.org/0000-0002-4742-0841"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Wolf","raw_affiliation_strings":["Princeton University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"542","last_page":"547"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.828122615814209},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7131384611129761},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6326561570167542},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5188349485397339},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.47395873069763184},{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.46328964829444885},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4552208483219147},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4086701273918152},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32885393500328064},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3103640377521515},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18426653742790222},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.12511637806892395}],"concepts":[{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.828122615814209},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7131384611129761},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6326561570167542},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5188349485397339},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.47395873069763184},{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.46328964829444885},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4552208483219147},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4086701273918152},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32885393500328064},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3103640377521515},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18426653742790222},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.12511637806892395},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2003.1253665","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2003.1253665","pdf_url":null,"source":{"id":"https://openalex.org/S4363607952","display_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1588594383","https://openalex.org/W1604826642","https://openalex.org/W2032094184","https://openalex.org/W2097065626","https://openalex.org/W2097371076","https://openalex.org/W2110759479","https://openalex.org/W2121424172","https://openalex.org/W2125515824","https://openalex.org/W2144931347","https://openalex.org/W2156141410","https://openalex.org/W2175304030","https://openalex.org/W2725179571","https://openalex.org/W4247998816","https://openalex.org/W6633127185","https://openalex.org/W6636304122"],"related_works":["https://openalex.org/W2289987414","https://openalex.org/W2386114299","https://openalex.org/W2766876417","https://openalex.org/W2347291799","https://openalex.org/W2027050626","https://openalex.org/W2949851887","https://openalex.org/W4386582991","https://openalex.org/W2376421566","https://openalex.org/W2352986872","https://openalex.org/W4321844105"],"abstract_inverted_index":{"Signal":[0],"integrity":[1],"is":[2],"and":[3,29,59,92,117,131],"will":[4,50],"continue":[5],"to":[6,24,113],"be":[7,51],"a":[8,62,71,89,93,103,132],"major":[9],"concern":[10],"in":[11,120],"deep":[12],"sub-micron":[13],"VLSI":[14],"designs":[15],"where":[16],"the":[17],"proximity":[18],"of":[19,65,74,98,102,106,122,124],"signal":[20,27,47,66],"carrying":[21,48],"lines":[22,49,87,129],"leads":[23],"crosstalk,":[25],"unpredictable":[26],"delays":[28],"other":[30,114],"parasitic":[31],"side":[32],"effects.":[33],"Our":[34],"scheme":[35,112],"uses":[36],"bus":[37,78],"encoding":[38],"that":[39,41],"guarantees":[40],"at":[42,54,70],"any":[43,45],"time":[44],"two":[46],"separated":[52],"by":[53],"least":[55],"one":[56,76],"grounded":[57],"line":[58,79],"thus":[60],"providing":[61],"high":[63],"degree":[64,123],"integrity.":[67],"This":[68],"comes":[69],"small":[72,94],"overhead":[73,126],"only":[75],"additional":[77,86,128],"(the":[80],"closest":[81],"related":[82],"work":[83],"needs":[84],"14":[85],"for":[88],"32-bit":[90],"bus)":[91],"average":[95],"performance":[96,134],"decrease":[97],"0.36%.":[99],"By":[100],"means":[101],"large":[104],"set":[105],"real-world":[107],"applications,":[108],"we":[109],"compare":[110],"our":[111],"state-of-the-art":[115],"approaches":[116],"present":[118],"comparisons":[119],"terms":[121],"integrity,":[125],"(e.g.":[127],"required)":[130],"possible":[133],"decrease.":[135]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}