{"id":"https://openalex.org/W2151328753","doi":"https://doi.org/10.1109/date.2003.1186689","title":"A flexible virtual platform for computational and communication architecture exploration of DMT VDSL modems","display_name":"A flexible virtual platform for computational and communication architecture exploration of DMT VDSL modems","publication_year":2003,"publication_date":"2003-12-22","ids":{"openalex":"https://openalex.org/W2151328753","doi":"https://doi.org/10.1109/date.2003.1186689","mag":"2151328753"},"language":"en","primary_location":{"id":"doi:10.1109/date.2003.1186689","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2003.1186689","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021808967","display_name":"S. Brini","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"S. Brini","raw_affiliation_strings":["Advanced System Technology, STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced System Technology, STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070883941","display_name":"D. Benjelloun","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"D. Benjelloun","raw_affiliation_strings":["Advanced System Technology, STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced System Technology, STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063602056","display_name":"F. Castanier","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"F. Castanier","raw_affiliation_strings":["Advanced System Technology, STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced System Technology, STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210104693"],"apc_list":null,"apc_paid":null,"fwci":1.1655,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.78404972,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"164","last_page":"169"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7014485001564026},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.656281054019928},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5879641175270081},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5380114912986755},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4669557511806488},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.453419029712677},{"id":"https://openalex.org/keywords/digital-subscriber-line","display_name":"Digital subscriber line","score":0.4151081442832947},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.348031222820282},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20696181058883667}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7014485001564026},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.656281054019928},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5879641175270081},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5380114912986755},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4669557511806488},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.453419029712677},{"id":"https://openalex.org/C201374245","wikidata":"https://www.wikidata.org/wiki/Q104534","display_name":"Digital subscriber line","level":2,"score":0.4151081442832947},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.348031222820282},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20696181058883667},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/date.2003.1186689","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2003.1186689","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.125.6603","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.125.6603","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://date.eda-online.co.uk/proceedings/papers/2003/date03/df_files/04d_2.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2037070852","https://openalex.org/W2119327381","https://openalex.org/W2150427624","https://openalex.org/W2151415616","https://openalex.org/W2158794435","https://openalex.org/W2170077922","https://openalex.org/W4232048937"],"related_works":["https://openalex.org/W1550409889","https://openalex.org/W1830510111","https://openalex.org/W2039065447","https://openalex.org/W2208074837","https://openalex.org/W1581055755","https://openalex.org/W2102117846","https://openalex.org/W2132074508","https://openalex.org/W2149449165","https://openalex.org/W4256613086","https://openalex.org/W4238487776"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"a":[3,66],"high-level":[4],"SoC":[5],"architecture":[6,99],"exploration":[7,72],"of":[8,36,38,47,62,73,80,95],"DMT":[9],"(Discrete":[10],"Multitone)":[11],"VDSL":[12],"transceivers":[13],"(Very":[14],"high":[15],"speed":[16],"Digital":[17],"Subscriber":[18],"Line)":[19],"is":[20],"presented.":[21],"A":[22,85],"flexible":[23],"and":[24,77,100],"complete":[25],"virtual":[26],"platform":[27],"was":[28,90],"developed":[29,91],"for":[30,92],"the":[31,34,45,60,71,78,81,93,96],"purpose,":[32],"exploiting":[33],"paradigm":[35],"\"orthogonalization":[37],"concerns\"":[39],"(functionality":[40],"independent":[41],"from":[42],"architecture)":[43],"in":[44],"framework":[46],"Cadence":[48],"VCC":[49,87],"system":[50],"level":[51],"design":[52],"tool.":[53],"An":[54],"accurate":[55],"processor":[56],"model,":[57],"obtained":[58],"through":[59],"back-annotation":[61],"profiling":[63],"results":[64],"on":[65],"target":[67],"DSP":[68],"core,":[69],"allowed":[70],"different":[74],"HW/SW":[75],"partitioning":[76],"study":[79],"computational":[82],"units":[83],"required.":[84],"transaction-accurate":[86],"bus":[88,98],"model":[89],"investigation":[94],"on-chip":[97],"its":[101],"relevant":[102],"parameters":[103],"dimensioning.":[104]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}
