{"id":"https://openalex.org/W2156922370","doi":"https://doi.org/10.1109/date.2003.1186679","title":"SystemC-VHDL co-simulation and synthesis in the HW domain","display_name":"SystemC-VHDL co-simulation and synthesis in the HW domain","publication_year":2003,"publication_date":"2003-12-22","ids":{"openalex":"https://openalex.org/W2156922370","doi":"https://doi.org/10.1109/date.2003.1186679","mag":"2156922370"},"language":"en","primary_location":{"id":"doi:10.1109/date.2003.1186679","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2003.1186679","pdf_url":null,"source":{"id":"https://openalex.org/S4363607952","display_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052422346","display_name":"M. Bombana","orcid":null},"institutions":[{"id":"https://openalex.org/I4210142603","display_name":"Siemens (Italy)","ror":"https://ror.org/04f6ygk28","country_code":"IT","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210142603"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M. Bombana","raw_affiliation_strings":["Siemens MC S.p.A., Italy"],"affiliations":[{"raw_affiliation_string":"Siemens MC S.p.A., Italy","institution_ids":["https://openalex.org/I4210142603"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058243151","display_name":"F. Bruschi","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Bruschi","raw_affiliation_strings":["Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5052422346"],"corresponding_institution_ids":["https://openalex.org/I4210142603"],"apc_list":null,"apc_paid":null,"fwci":1.0248,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.72055427,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"101","last_page":"105"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9876686930656433},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8381615877151489},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.717383623123169},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6433588266372681},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.6113015413284302},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5606355667114258},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5061365962028503},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.502155065536499},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4941003620624542},{"id":"https://openalex.org/keywords/novelty","display_name":"Novelty","score":0.45181989669799805},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.45116758346557617},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.44372260570526123},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42810872197151184},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.27882903814315796}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9876686930656433},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8381615877151489},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.717383623123169},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6433588266372681},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.6113015413284302},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5606355667114258},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5061365962028503},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.502155065536499},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4941003620624542},{"id":"https://openalex.org/C2778738651","wikidata":"https://www.wikidata.org/wiki/Q16546687","display_name":"Novelty","level":2,"score":0.45181989669799805},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.45116758346557617},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.44372260570526123},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42810872197151184},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.27882903814315796},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C27206212","wikidata":"https://www.wikidata.org/wiki/Q34178","display_name":"Theology","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/date.2003.1186679","is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2003.1186679","pdf_url":null,"source":{"id":"https://openalex.org/S4363607952","display_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2003 Design, Automation and Test in Europe Conference and Exhibition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2544073398","https://openalex.org/W1831349210","https://openalex.org/W2548514518","https://openalex.org/W2379408401","https://openalex.org/W2106574988","https://openalex.org/W2802530065","https://openalex.org/W2359630088","https://openalex.org/W1996778651","https://openalex.org/W1603163876","https://openalex.org/W2133642747"],"abstract_inverted_index":{"Embedded":[0],"systems":[1],"design":[2,30,44,88],"requires":[3],"the":[4,13,19,23,66,104,114,118,123],"development":[5],"of":[6,18,43,46,73,113,122],"complex":[7],"HW":[8,29,47],"modules":[9,48],"to":[10,25,32,60,68,102],"cope":[11],"with":[12],"most":[14],"stringent":[15],"timing":[16],"constraints":[17],"specifications.":[20],"This":[21],"implies":[22],"need":[24],"update":[26],"and":[27,35,53,71,76,108,120],"enrich":[28],"methodologies":[31],"face":[33],"abstraction":[34,63],"novel":[36],"requirements.":[37],"Here":[38],"we":[39],"present":[40],"some":[41],"results":[42],"practice":[45],"in":[49,57,65,84],"this":[50,58],"context.":[51],"Co-simulation":[52],"synthesis":[54],"are":[55],"combined":[56],"approach":[59],"achieve":[61],"higher":[62],"levels":[64],"design,":[67],"improve":[69],"validation":[70],"re-use":[72],"previous":[74],"designs":[75],"human":[77],"experience.":[78],"The":[79,90,110],"proposed":[80],"methodology":[81],"is":[82,94],"embedded":[83],"a":[85,98],"SystemC":[86],"based":[87,96],"flow.":[89],"SystemC-VHDL":[91],"co-simulator":[92],"tool":[93],"also":[95],"on":[97],"SystemC/C++":[99],"front-end":[100],"developed":[101],"support":[103],"co-simulation":[105],"between":[106],"VHDL":[107],"SystemC.":[109],"prototypal":[111],"state":[112],"adopted":[115],"tools":[116],"increase":[117],"novelty":[119],"interest":[121],"approach.":[124]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}