{"id":"https://openalex.org/W2772034915","doi":"https://doi.org/10.1109/dasip.2017.8122108","title":"LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs","display_name":"LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2772034915","doi":"https://doi.org/10.1109/dasip.2017.8122108","mag":"2772034915"},"language":"en","primary_location":{"id":"doi:10.1109/dasip.2017.8122108","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2017.8122108","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014794132","display_name":"Marc Reichenbach","orcid":"https://orcid.org/0000-0002-9687-6247"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Marc Reichenbach","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002208253","display_name":"Philipp Holzinger","orcid":"https://orcid.org/0000-0002-2912-0650"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Philipp Holzinger","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090573570","display_name":"Konrad H\u00e4ublein","orcid":null},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Konrad Haublein","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012029717","display_name":"Tobias Lieske","orcid":"https://orcid.org/0000-0002-6114-015X"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Tobias Lieske","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061368393","display_name":"Paul Blinzer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul Blinzer","raw_affiliation_strings":["Advanced Micro Devices (AMD), Bellevue, WA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices (AMD), Bellevue, WA","institution_ids":["https://openalex.org/I4210137977"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030918623","display_name":"Dietmar Fey","orcid":"https://orcid.org/0000-0002-6077-4732"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dietmar Fey","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander-University, Erlangen- Nuremberg, Germany","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8113924860954285},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.705898642539978},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.5859644412994385},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5814302563667297},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5455211997032166},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5376577973365784},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.5306011438369751},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.473088800907135},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4709404706954956},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45470577478408813},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3692966401576996},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3403138816356659},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24867263436317444}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8113924860954285},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.705898642539978},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.5859644412994385},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5814302563667297},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5455211997032166},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5376577973365784},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.5306011438369751},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.473088800907135},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4709404706954956},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45470577478408813},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3692966401576996},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3403138816356659},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24867263436317444}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dasip.2017.8122108","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2017.8122108","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1492601037","https://openalex.org/W1554962108","https://openalex.org/W1555915743","https://openalex.org/W1967524458","https://openalex.org/W2012295523","https://openalex.org/W2037748535","https://openalex.org/W2146411490","https://openalex.org/W2283605469","https://openalex.org/W2344065022","https://openalex.org/W2416330002","https://openalex.org/W2483849769","https://openalex.org/W2575648231","https://openalex.org/W4241765343","https://openalex.org/W6732268051"],"related_works":["https://openalex.org/W4383503138","https://openalex.org/W3131592046","https://openalex.org/W2075931580","https://openalex.org/W3115530580","https://openalex.org/W2622392763","https://openalex.org/W3214999411","https://openalex.org/W1975561105","https://openalex.org/W4391536292","https://openalex.org/W4214905828","https://openalex.org/W2081510580"],"abstract_inverted_index":{"Various":[0],"signal":[1],"and":[2,15,77,103,116,157],"image":[3,169,177],"processing":[4,14],"applications":[5,24,36],"require":[6],"vast":[7],"acceleration":[8],"in":[9,18,45,53],"order":[10],"to":[11,89,146],"enable":[12],"real-time":[13],"meet":[16],"constraints":[17],"power":[19],"consumption.":[20],"On":[21],"FPGAs":[22,49],"these":[23,40],"can":[25],"be":[26],"implemented":[27],"as":[28,98],"application-specific":[29],"circuit.":[30],"Although":[31],"IP":[32,127],"cores":[33],"for":[34,68,94,101,211],"various":[35],"exist,":[37],"even":[38],"interfacing":[39],"usually":[41],"requires":[42],"experienced":[43],"knowledge":[44],"hardware":[46,67,135,196,214],"design.":[47],"Using":[48],"or":[50,186],"other":[51,117],"accelerators":[52,145,197],"a":[54,58,69,91,99,167,173,191],"heterogeneous":[55,95,106],"system":[56,96],"from":[57,79,108],"host":[59],"CPU":[60],"would":[61],"simplify":[62],"the":[63,82,150,162,199,208],"usage":[64],"of":[65,134,149,164],"accelerator":[66,136],"common":[70],"software":[71],"developer.":[72],"Recognizing":[73],"this,":[74],"several":[75],"companies":[76],"partners":[78],"academia":[80],"created":[81],"HSA":[83,140,152,217],"Foundation":[84],"(Heterogeneous":[85],"System":[86],"Architecture":[87],"Foundation)":[88],"define":[90],"platform":[92],"specification":[93],"requirements":[97],"macro-architecture":[100],"efficient":[102],"easy":[104],"targeting":[105],"processors":[107],"popular":[109],"high-level":[110],"languages":[111],"like":[112],"C/C++,":[113],"Python,":[114],"Java":[115],"domain":[118],"specific":[119],"languages.":[120],"In":[121],"this":[122],"paper":[123],"we":[124],"present":[125],"an":[126,216],"library":[128,206],"(LibHSA),":[129],"that":[130],"greatly":[131],"simplifies":[132],"integration":[133],"functions":[137],"into":[138,215],"existing":[139,151],"compliant":[141,218],"systems.":[142],"This":[143],"allows":[144],"take":[147],"advantage":[148],"programming":[153],"model,":[154],"libraries,":[155],"compilers":[156],"toolchains.":[158],"We":[159],"will":[160],"demonstrate":[161],"work":[163],"LibHSA":[165,200],"utilizing":[166],"programmable":[168],"processor":[170,178],"implementation":[171],"on":[172],"Xilinx":[174],"FPGA.":[175],"The":[176],"supports":[179],"low-level":[180],"algorithms,":[181],"e.g.":[182],"Sobel,":[183],"Median,":[184],"Laplace,":[185],"Gauss.":[187],"Our":[188],"results":[189],"show":[190],"substantial":[192],"decrease":[193],"integrating":[194,212],"customized":[195],"using":[198],"infrastructure.":[201],"To":[202],"our":[203,205],"knowledge,":[204],"is":[207],"first":[209],"approach":[210],"reconfigurable":[213],"system.":[219]},"counts_by_year":[{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}