{"id":"https://openalex.org/W2587913377","doi":"https://doi.org/10.1109/dasip.2016.7853798","title":"SystemC modelling of lossless compression IP cores for space applications","display_name":"SystemC modelling of lossless compression IP cores for space applications","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2587913377","doi":"https://doi.org/10.1109/dasip.2016.7853798","mag":"2587913377"},"language":"en","primary_location":{"id":"doi:10.1109/dasip.2016.7853798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2016.7853798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069280017","display_name":"Lucana Santos","orcid":"https://orcid.org/0000-0001-5191-2673"},"institutions":[{"id":"https://openalex.org/I119635470","display_name":"Universidad de Las Palmas de Gran Canaria","ror":"https://ror.org/01teme464","country_code":"ES","type":"education","lineage":["https://openalex.org/I119635470"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Lucana Santos","raw_affiliation_strings":["Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Spain","institution_ids":["https://openalex.org/I119635470"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102256438","display_name":"Ana Gomez","orcid":null},"institutions":[{"id":"https://openalex.org/I119635470","display_name":"Universidad de Las Palmas de Gran Canaria","ror":"https://ror.org/01teme464","country_code":"ES","type":"education","lineage":["https://openalex.org/I119635470"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ana Gomez","raw_affiliation_strings":["Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Spain","institution_ids":["https://openalex.org/I119635470"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075819214","display_name":"Pedro Hern\u00e1ndez-Fern\u00e1ndez","orcid":"https://orcid.org/0000-0003-3848-2116"},"institutions":[{"id":"https://openalex.org/I119635470","display_name":"Universidad de Las Palmas de Gran Canaria","ror":"https://ror.org/01teme464","country_code":"ES","type":"education","lineage":["https://openalex.org/I119635470"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Hernandez-Fernandez","raw_affiliation_strings":["Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Spain","institution_ids":["https://openalex.org/I119635470"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047871791","display_name":"Roberto Sarmiento","orcid":"https://orcid.org/0000-0002-4843-0507"},"institutions":[{"id":"https://openalex.org/I119635470","display_name":"Universidad de Las Palmas de Gran Canaria","ror":"https://ror.org/01teme464","country_code":"ES","type":"education","lineage":["https://openalex.org/I119635470"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Roberto Sarmiento","raw_affiliation_strings":["Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Spain","institution_ids":["https://openalex.org/I119635470"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I119635470"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.18783121,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"65","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8398005962371826},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8362200856208801},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.700831413269043},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6243590712547302},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5724366307258606},{"id":"https://openalex.org/keywords/lossless-compression","display_name":"Lossless compression","score":0.5630173683166504},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5568853616714478},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5436332821846008},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42502039670944214},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.4104262590408325},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33383995294570923},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21499502658843994}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8398005962371826},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8362200856208801},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.700831413269043},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6243590712547302},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5724366307258606},{"id":"https://openalex.org/C81081738","wikidata":"https://www.wikidata.org/wiki/Q55542","display_name":"Lossless compression","level":3,"score":0.5630173683166504},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5568853616714478},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5436332821846008},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42502039670944214},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.4104262590408325},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33383995294570923},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21499502658843994}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dasip.2016.7853798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2016.7853798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","raw_type":"proceedings-article"},{"id":"pmh:oai:accedacris.ulpgc.es:10553/44979","is_oa":false,"landing_page_url":"http://hdl.handle.net/10553/44979","pdf_url":null,"source":{"id":"https://openalex.org/S4306400136","display_name":"Acceda (Universidad de Las Palmas de Gran Canaria)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Conference on Design and Architectures for Signal and Image Processing, DASIP[ISSN 2164-9766] (7853798), p. 65-72","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1964647277","https://openalex.org/W2058606860","https://openalex.org/W2329053551","https://openalex.org/W2481725867","https://openalex.org/W4247806563"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W2119904701","https://openalex.org/W1984090905","https://openalex.org/W4234221021","https://openalex.org/W2548514518","https://openalex.org/W1917852300","https://openalex.org/W2170029576","https://openalex.org/W2159088510","https://openalex.org/W2790192245","https://openalex.org/W2384838054"],"abstract_inverted_index":{"In":[0,26,76],"this":[1,153],"paper,":[2],"we":[3,28,199],"perform":[4,200],"the":[5,23,30,38,44,77,80,83,88,95,118,160,166,176,196,204,208,214,219,230,269,283],"Electronic":[6],"System":[7],"Level":[8],"(ESL)":[9],"modelling":[10,246],"and":[11,32,43,50,63,103,130,210,225],"verification":[12],"of":[13,37,87,94,126,152,159,168,203,218,229],"two":[14],"lossless":[15,41,46],"compression":[16,134],"standard":[17],"algorithms":[18,54,119,135,177],"for":[19,48,170],"space":[20],"applications":[21],"using":[22,244],"SystemC":[24,36,197,275],"language.":[25],"particular":[27],"present":[29],"architectures":[31,111],"a":[33,99,171,182,259],"description":[34],"in":[35,120,124,162,181,216,251,288],"CCSDS-121":[39,81],"universal":[40],"compressor":[42,47],"CCSDS-123":[45,89],"hyperspectral":[49],"multispectral":[51],"images.":[52],"Both":[53],"were":[55],"specifically":[56],"designed":[57],"to":[58,108,116,146,156,240,281],"operate":[59],"on":[60,98,139],"board":[61],"satellites":[62],"they":[64],"can":[65,188,278],"be":[66,179,189,279],"utilized":[67],"as":[68,72,74,262,264],"independent":[69],"standalone":[70],"compressors":[71,161],"well":[73,263],"jointly.":[75],"latter":[78],"case,":[79],"performs":[82],"entropy":[84],"coding":[85],"stage":[86],"compressor.":[90],"The":[91,149,234],"computational":[92],"capabilities":[93],"hardware":[96,110,183,227],"available":[97],"satellite":[100],"are":[101,136,144,271],"limited,":[102],"hence,":[104],"it":[105,114],"is":[106,155],"necessary":[107],"design":[109,184,205],"that":[112,143,164,187,256,277],"make":[113],"possible":[115],"execute":[117],"an":[121,201,252],"efficient":[122],"way":[123],"terms":[125],"throughput,":[127],"resource":[128],"utilization":[129],"power":[131],"consumption.":[132],"On-board":[133],"usually":[137],"implemented":[138],"ASICs":[140],"or":[141],"FPGAs":[142],"tolerant":[145],"solar":[147],"radiation.":[148],"main":[150],"objective":[151],"work":[154],"describe":[157],"models":[158,236,270],"SystemC,":[163],"enable":[165],"generation":[167],"specifications":[169],"subsequent":[172],"implementation":[173],"phase":[174],"where":[175],"will":[178],"described":[180,235,287],"language":[185],"(VHDL)":[186],"efficiently":[190],"mapped":[191],"into":[192],"space-qualified":[193],"FPGAs.":[194],"With":[195],"models,":[198],"exploration":[202],"space,":[206],"refining":[207],"architecture,":[209],"retrieving":[211],"information":[212],"about":[213],"limits":[215],"performance":[217],"cores,":[220],"storage":[221],"requirements,":[222],"data":[223],"dependencies":[224],"prospective":[226],"requirements":[228],"later":[231],"FPGA":[232],"implementation.":[233],"also":[237],"comprise":[238],"connections":[239],"shared":[241],"communication":[242],"buses":[243],"transaction-level":[245],"(TLM),":[247],"allowing":[248],"their":[249],"inclusion":[250],"embedded":[253],"system":[254],"model":[255],"may":[257],"include":[258],"software":[260],"co-processor":[261],"other":[265],"processing":[266],"cores.":[267],"Additionally,":[268],"verified":[272],"by":[273],"creating":[274],"testbenches":[276],"reused":[280],"verify":[282],"IP":[284],"cores":[285],"when":[286],"VHDL.":[289]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}