{"id":"https://openalex.org/W1588159406","doi":"https://doi.org/10.1109/dasip.2014.7115628","title":"Low-cost guaranteed-throughput dual-ring communication infrastructure for heterogeneous MPSoCs","display_name":"Low-cost guaranteed-throughput dual-ring communication infrastructure for heterogeneous MPSoCs","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W1588159406","doi":"https://doi.org/10.1109/dasip.2014.7115628","mag":"1588159406"},"language":"en","primary_location":{"id":"doi:10.1109/dasip.2014.7115628","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2014.7115628","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069726596","display_name":"Berend H.J. Dekens","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Berend H.J. Dekens","raw_affiliation_strings":["Department of EEMCS, University of Twente, Enschede, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of EEMCS, University of Twente, Enschede, The Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108358746","display_name":"Philip S. Wilmanns","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Philip S. Wilmanns","raw_affiliation_strings":["Department of EEMCS, University of Twente, Enschede, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of EEMCS, University of Twente, Enschede, The Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111430194","display_name":"Gerard J.M. Smit","orcid":"https://orcid.org/0000-0002-8595-0106"},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Gerard J.M. Smit","raw_affiliation_strings":["Department of EEMCS, University of Twente, Enschede, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of EEMCS, University of Twente, Enschede, The Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111443523","display_name":"Marco J.G. Bekooij","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]},{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Marco J.G. Bekooij","raw_affiliation_strings":["Department of EEMCS, University of Twente, Enschede, The Netherlands","NXP Semiconductors, Eindhoven, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of EEMCS, University of Twente, Enschede, The Netherlands","institution_ids":["https://openalex.org/I94624287"]},{"raw_affiliation_string":"NXP Semiconductors, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I109147379"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5069726596"],"corresponding_institution_ids":["https://openalex.org/I94624287"],"apc_list":null,"apc_paid":null,"fwci":0.6896,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72024144,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"761","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.9742714166641235},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6906853914260864},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6818407773971558},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.645656168460846},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5944976806640625},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5852367877960205},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5401806235313416},{"id":"https://openalex.org/keywords/stream-processing","display_name":"Stream processing","score":0.4395591616630554},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.42359262704849243},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35409384965896606},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3214288055896759},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.25853708386421204},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.19012418389320374},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14682230353355408}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.9742714166641235},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6906853914260864},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6818407773971558},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.645656168460846},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5944976806640625},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5852367877960205},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5401806235313416},{"id":"https://openalex.org/C107027933","wikidata":"https://www.wikidata.org/wiki/Q2006448","display_name":"Stream processing","level":2,"score":0.4395591616630554},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.42359262704849243},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35409384965896606},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3214288055896759},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.25853708386421204},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19012418389320374},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14682230353355408},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/dasip.2014.7115628","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2014.7115628","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing","raw_type":"proceedings-article"},{"id":"pmh:oai:ris.utwente.nl:openaire_cris_publications/3a930c78-cf87-4b7b-99b1-d20f55aa2e88","is_oa":false,"landing_page_url":"https://research.utwente.nl/en/publications/3a930c78-cf87-4b7b-99b1-d20f55aa2e88","pdf_url":null,"source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Dekens, B H J, Kurtin, P S, Smit, G J M & Bekooij, M J G 2014, Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs. in 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). ECSI Media, France, pp. 157-164, 2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, Madrid, Spain, 8/10/14. https://doi.org/10.1109/DASIP.2014.7115628, https://doi.org/10.13140/2.1.1522.9765","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:ris.utwente.nl:publications/3a930c78-cf87-4b7b-99b1-d20f55aa2e88","is_oa":false,"landing_page_url":"http://eprints.eemcs.utwente.nl/secure2/25173/01/dekens.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1531254150","https://openalex.org/W1603513077","https://openalex.org/W2012959791","https://openalex.org/W2034147186","https://openalex.org/W2062190012","https://openalex.org/W2070385897","https://openalex.org/W2079726719","https://openalex.org/W2081590538","https://openalex.org/W2088479706","https://openalex.org/W2096856647","https://openalex.org/W2109369875","https://openalex.org/W2125028861","https://openalex.org/W2139522402","https://openalex.org/W2164042340","https://openalex.org/W2295846064","https://openalex.org/W2398913158","https://openalex.org/W2533425045","https://openalex.org/W3144593894","https://openalex.org/W4233983581","https://openalex.org/W4236433846","https://openalex.org/W4254440925","https://openalex.org/W6631883425","https://openalex.org/W6636000386","https://openalex.org/W6671231407","https://openalex.org/W6697392258"],"related_works":["https://openalex.org/W1976012348","https://openalex.org/W2614713859","https://openalex.org/W2002682434","https://openalex.org/W4387782849","https://openalex.org/W2137671689","https://openalex.org/W2113449380","https://openalex.org/W2012131147","https://openalex.org/W3146394219","https://openalex.org/W2157008728","https://openalex.org/W2016942572"],"abstract_inverted_index":{"Connection-oriented":[0],"Guaranteed-Throughput":[1],"(GT)":[2],"mesh-based":[3],"Networks":[4],"on":[5,58,146],"Chip":[6,59],"(NoCs)":[7],"have":[8],"been":[9],"proposed":[10],"as":[11,26,45],"a":[12,40,46,78,107,114,139,147,153,164],"replacement":[13],"for":[14,49,82,113],"buses":[15],"in":[16,51,138,172],"real-time":[17,154],"stream":[18,65],"processing":[19,66],"systems":[20],"but":[21],"are":[22,89,127],"currently":[23],"rarely":[24],"used":[25],"hardware":[27,173],"cost":[28,174],"tends":[29],"to":[30],"be":[31],"higher":[32],"than":[33],"conventional":[34],"interconnects.":[35],"Recently":[36],"an":[37,70,136,170],"interconnect":[38],"with":[39,116],"ring":[41,74,134],"topology":[42],"was":[43,167],"introduced":[44],"low-cost":[47],"alternative":[48],"use":[50],"medium":[52],"scale":[53],"homogeneous":[54],"Multiple":[55],"Processor":[56],"System":[57],"(MPSoC)":[60],"designs.":[61,85],"Cost-effective":[62],"integration":[63,130],"of":[64,72,106,131,163,175],"accelerators":[67,119],"would":[68],"require":[69],"extension":[71],"this":[73,151],"interconnect.":[75],"We":[76],"present":[77],"dual-ring":[79],"communication":[80,117],"infrastructure":[81],"heterogeneous":[83],"MPSoC":[84,142,152],"Data":[86,109],"and":[87,120,125,135],"credits":[88],"transferred":[90],"between":[91,118],"tiles":[92],"using":[93],"their":[94],"separate,":[95],"oppositely":[96],"directed,":[97],"rings.":[98],"The":[99,122],"minimum":[100],"throughput":[101],"is":[102,144,158],"determined":[103],"by":[104,129],"analysis":[105],"Cyclo-Static":[108],"Flow":[110],"(CSDF)":[111],"model":[112],"system":[115],"processors.":[121],"performance":[123,161],"benefits":[124],"costs":[126],"evaluated":[128],"our":[132],"dual":[133],"accelerator":[137],"16":[140],"core":[141],"which":[143],"mapped":[145],"Virtex6":[148],"FPGA.":[149],"On":[150],"PAL":[155],"video":[156],"decoder":[157],"executed.":[159],"A":[160],"gain":[162],"factor":[165],"3.6":[166],"obtained":[168],"at":[169],"increase":[171],"only":[176],"8.5%.":[177]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
