{"id":"https://openalex.org/W2028686533","doi":"https://doi.org/10.1109/dasip.2011.6136878","title":"Optimization methodologies for complex FPGA-based signal processing systems with CAL","display_name":"Optimization methodologies for complex FPGA-based signal processing systems with CAL","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W2028686533","doi":"https://doi.org/10.1109/dasip.2011.6136878","mag":"2028686533"},"language":"en","primary_location":{"id":"doi:10.1109/dasip.2011.6136878","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2011.6136878","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026822024","display_name":"Ab Al-Hadi Ab Rahman","orcid":"https://orcid.org/0000-0002-0754-5199"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Ab Al-Hadi Ab Rahman","raw_affiliation_strings":["SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054621269","display_name":"Hossam Amer","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Hossam Amer","raw_affiliation_strings":["SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027175391","display_name":"\u0410. \u0410. Prihozhy","orcid":"https://orcid.org/0000-0002-1941-0806"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Anatoly Prihozhy","raw_affiliation_strings":["SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037961095","display_name":"Christophe Lucarz","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Christophe Lucarz","raw_affiliation_strings":["SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013188524","display_name":"Marco Mattavelli","orcid":"https://orcid.org/0000-0002-7742-0332"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Marco Mattavelli","raw_affiliation_strings":["SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"SCI-STI-MM, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5026822024"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":0.7556,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72138971,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.8612114191055298},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8215752840042114},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7680933475494385},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.674523651599884},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6210129261016846},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5800117254257202},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4686673879623413},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.455261766910553},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4295957684516907},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4229086637496948},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.41637158393859863},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.404079794883728},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.3802996873855591},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28489822149276733},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1087363064289093}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.8612114191055298},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8215752840042114},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7680933475494385},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.674523651599884},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6210129261016846},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5800117254257202},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4686673879623413},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.455261766910553},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4295957684516907},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4229086637496948},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.41637158393859863},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.404079794883728},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.3802996873855591},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28489822149276733},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1087363064289093},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dasip.2011.6136878","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2011.6136878","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.550000011920929,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W202631676","https://openalex.org/W1738750393","https://openalex.org/W1849568040","https://openalex.org/W2103581911","https://openalex.org/W2115443376","https://openalex.org/W2117678124","https://openalex.org/W2122712122","https://openalex.org/W2129183345","https://openalex.org/W2132457452","https://openalex.org/W2137465482","https://openalex.org/W2157598146","https://openalex.org/W4235386637","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W1741246166","https://openalex.org/W1508949720","https://openalex.org/W1855080238","https://openalex.org/W2890557332","https://openalex.org/W3048824278","https://openalex.org/W3022644913","https://openalex.org/W2077629192","https://openalex.org/W2704801810","https://openalex.org/W2156483123","https://openalex.org/W2025571570"],"abstract_inverted_index":{"Signal":[0],"processing":[1],"designs":[2],"are":[3,14],"becoming":[4],"increasingly":[5],"complex":[6],"with":[7,134],"demands":[8],"for":[9,45,96,124],"more":[10],"advanced":[11],"algorithms.":[12],"Designers":[13],"now":[15],"seeking":[16],"high-level":[17],"tools":[18,104],"and":[19,25,48,82,101,105],"methodology":[20],"to":[21,80,107,139,146],"help":[22],"manage":[23],"complexity":[24],"increase":[26,70],"productivity.":[27],"Recently,":[28],"CAL":[29,84],"dataflow":[30,40],"language":[31],"has":[32,61],"been":[33,62],"specified":[34],"which":[35,68,88],"is":[36],"capable":[37],"of":[38,137],"synthesizing":[39],"description":[41],"into":[42],"RTL":[43],"codes":[44],"hardware":[46],"implementation,":[47],"based":[49],"on":[50,64,117,126],"several":[51],"case":[52,115],"studies,":[53],"have":[54],"shown":[55],"promising":[56],"results.":[57],"However,":[58],"no":[59],"work":[60],"done":[63],"global":[65],"network":[66],"analysis,":[67],"could":[69],"the":[71,97,118,147],"optimization":[72],"space.":[73],"In":[74],"this":[75,109],"paper,":[76],"we":[77],"introduce":[78],"methodologies":[79],"analyze":[81],"optimize":[83],"programs":[85],"by":[86],"determining":[87],"actions":[89],"should":[90],"be":[91],"parallelized,":[92],"pipelined,":[93],"or":[94],"refactored":[95],"highest":[98],"throughput":[99,135],"gain,":[100],"then":[102],"providing":[103],"techniques":[106],"achieve":[108],"using":[110,141],"minimum":[111],"resource.":[112],"As":[113],"a":[114],"study":[116],"RVC":[119],"MPEG-4":[120],"SP":[121],"Intra":[122],"decoder":[123],"implementation":[125],"Virtex-5":[127],"FPGA,":[128],"experimental":[129],"results":[130],"confirmed":[131],"our":[132],"analysis":[133],"gain":[136],"up":[138],"3.5x":[140],"relatively-minor":[142],"additional":[143],"slice":[144],"compared":[145],"reference":[148],"design.":[149]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}