{"id":"https://openalex.org/W2006428293","doi":"https://doi.org/10.1109/dasip.2011.6136850","title":"Design of a processor optimized for syntax parsing in video decoders","display_name":"Design of a processor optimized for syntax parsing in video decoders","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W2006428293","doi":"https://doi.org/10.1109/dasip.2011.6136850","mag":"2006428293"},"language":"en","primary_location":{"id":"doi:10.1109/dasip.2011.6136850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2011.6136850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026531279","display_name":"Nicolas Siret","orcid":null},"institutions":[{"id":"https://openalex.org/I126425946","display_name":"Universit\u00e9 Europ\u00e9enne de Bretagne","ror":"https://ror.org/033c46s90","country_code":"FR","type":"education","lineage":["https://openalex.org/I126425946"]},{"id":"https://openalex.org/I4210100151","display_name":"Institut d'\u00c9lectronique et des Technologies du num\u00e9Rique","ror":"https://ror.org/013q33h79","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I28221208","https://openalex.org/I4210095849","https://openalex.org/I4210100151","https://openalex.org/I56067802","https://openalex.org/I97188460"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Nicolas Siret","raw_affiliation_strings":["INSA, IETR, UMR 6164, European university of Brittany, Rennes, France","European University of Brittany, France, INSA, IETR, UMR 6164, F-35708 Rennes"],"affiliations":[{"raw_affiliation_string":"INSA, IETR, UMR 6164, European university of Brittany, Rennes, France","institution_ids":["https://openalex.org/I126425946","https://openalex.org/I4210100151"]},{"raw_affiliation_string":"European University of Brittany, France, INSA, IETR, UMR 6164, F-35708 Rennes","institution_ids":["https://openalex.org/I126425946","https://openalex.org/I4210100151"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041007136","display_name":"Jean-Fran\u00e7ois Nezan","orcid":"https://orcid.org/0000-0002-0609-4592"},"institutions":[{"id":"https://openalex.org/I4210100151","display_name":"Institut d'\u00c9lectronique et des Technologies du num\u00e9Rique","ror":"https://ror.org/013q33h79","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I28221208","https://openalex.org/I4210095849","https://openalex.org/I4210100151","https://openalex.org/I56067802","https://openalex.org/I97188460"]},{"id":"https://openalex.org/I126425946","display_name":"Universit\u00e9 Europ\u00e9enne de Bretagne","ror":"https://ror.org/033c46s90","country_code":"FR","type":"education","lineage":["https://openalex.org/I126425946"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean-Francois Nezan","raw_affiliation_strings":["INSA, IETR, UMR 6164, European university of Brittany, Rennes, France","European University of Brittany, France, INSA, IETR, UMR 6164, F-35708 Rennes"],"affiliations":[{"raw_affiliation_string":"INSA, IETR, UMR 6164, European university of Brittany, Rennes, France","institution_ids":["https://openalex.org/I126425946","https://openalex.org/I4210100151"]},{"raw_affiliation_string":"European University of Brittany, France, INSA, IETR, UMR 6164, F-35708 Rennes","institution_ids":["https://openalex.org/I126425946","https://openalex.org/I4210100151"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034449609","display_name":"Aimad Rhatay","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Aimad Rhatay","raw_affiliation_strings":["Lead Tech Design, Rennes, France","Lead Tech Design, F-35700 Rennes, France"],"affiliations":[{"raw_affiliation_string":"Lead Tech Design, Rennes, France","institution_ids":[]},{"raw_affiliation_string":"Lead Tech Design, F-35700 Rennes, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5026531279"],"corresponding_institution_ids":["https://openalex.org/I126425946","https://openalex.org/I4210100151"],"apc_list":null,"apc_paid":null,"fwci":0.24167956,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54133635,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"3311","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8436856865882874},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.8329236507415771},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8115216493606567},{"id":"https://openalex.org/keywords/parsing","display_name":"Parsing","score":0.6847780346870422},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5678876638412476},{"id":"https://openalex.org/keywords/nios-ii","display_name":"Nios II","score":0.5455084443092346},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5171689391136169},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5130318403244019},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48069578409194946},{"id":"https://openalex.org/keywords/syntax","display_name":"Syntax","score":0.47364652156829834},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.44536155462265015},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.42015576362609863},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4142623543739319},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3938666880130768},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17315134406089783},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12044212222099304}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8436856865882874},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.8329236507415771},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8115216493606567},{"id":"https://openalex.org/C186644900","wikidata":"https://www.wikidata.org/wiki/Q194152","display_name":"Parsing","level":2,"score":0.6847780346870422},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5678876638412476},{"id":"https://openalex.org/C2781190120","wikidata":"https://www.wikidata.org/wiki/Q438281","display_name":"Nios II","level":3,"score":0.5455084443092346},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5171689391136169},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5130318403244019},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48069578409194946},{"id":"https://openalex.org/C60048249","wikidata":"https://www.wikidata.org/wiki/Q37437","display_name":"Syntax","level":2,"score":0.47364652156829834},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.44536155462265015},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.42015576362609863},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4142623543739319},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3938666880130768},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17315134406089783},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12044212222099304},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dasip.2011.6136850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2011.6136850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1511666648","https://openalex.org/W1682189154","https://openalex.org/W1950331321","https://openalex.org/W1967767709","https://openalex.org/W2015863392","https://openalex.org/W2029823978","https://openalex.org/W2030843004","https://openalex.org/W2116353922","https://openalex.org/W2117678124","https://openalex.org/W2127124180","https://openalex.org/W2139402936","https://openalex.org/W2153218371","https://openalex.org/W2245938873","https://openalex.org/W2263577897","https://openalex.org/W2301074616","https://openalex.org/W6658073312","https://openalex.org/W6680612316","https://openalex.org/W7048792495"],"related_works":["https://openalex.org/W2047885859","https://openalex.org/W2036206036","https://openalex.org/W2189543321","https://openalex.org/W2551798393","https://openalex.org/W2900306051","https://openalex.org/W3002622661","https://openalex.org/W1861742280","https://openalex.org/W2031976241","https://openalex.org/W2125485192","https://openalex.org/W3160983798"],"abstract_inverted_index":{"Heterogeneous":[0],"platforms":[1,25],"aim":[2],"to":[3,48,67],"offer":[4],"both":[5,71],"performance":[6,46,69,106],"and":[7,13,83,102],"flexibility":[8],"by":[9],"providing":[10],"designers":[11],"processors":[12,39],"programmable":[14],"logical":[15],"units":[16],"on":[17,23,92],"a":[18,72,84,93,97],"single":[19],"platform.":[20],"Processors":[21],"implemented":[22],"these":[24,38],"are":[26],"usually":[27],"soft-cores":[28],"(e.g.":[29,34],"Altera":[30],"NIOS)":[31],"or":[32],"ASIC":[33],"ARM":[35],"Cortex-A8).":[36],"However,":[37],"still":[40],"face":[41],"limitations":[42],"in":[43,52,61],"terms":[44],"of":[45,99],"compared":[47],"full":[49],"hardware":[50],"designs":[51],"particular":[53],"for":[54,75],"real-time":[55],"video":[56],"decoding":[57],"applications.":[58],"We":[59],"present":[60],"this":[62],"paper":[63],"an":[64,112],"innovative":[65],"approach":[66],"improve":[68],"using":[70],"processor":[73],"optimized":[74],"the":[76,105],"syntax":[77],"parsing":[78],"(an":[79],"Application-Specific":[80],"Instruction-set":[81],"Processor)":[82],"FPGA.":[85],"The":[86],"case":[87],"study":[88],"has":[89],"been":[90],"synthesized":[91],"Xilinx":[94],"FPGA":[95],"at":[96],"frequency":[98],"100":[100],"MHz":[101],"we":[103],"estimate":[104],"that":[107],"could":[108],"be":[109],"obtained":[110],"with":[111],"ASIC.":[113]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}