{"id":"https://openalex.org/W2136226516","doi":"https://doi.org/10.1109/dasip.2010.5706271","title":"Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems","display_name":"Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems","publication_year":2010,"publication_date":"2010-10-01","ids":{"openalex":"https://openalex.org/W2136226516","doi":"https://doi.org/10.1109/dasip.2010.5706271","mag":"2136226516"},"language":"en","primary_location":{"id":"doi:10.1109/dasip.2010.5706271","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2010.5706271","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/10400.21/12300","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091017679","display_name":"Tiago Dias","orcid":"https://orcid.org/0000-0001-7445-5823"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Tiago Dias","raw_affiliation_strings":["INESC-ID Lisbon, ISEL-PI Lisbon, Technical University of Lisbon, IST, Lisboa, Portugal","INESC-ID Lisbon, ISEL-PI Lisbon, IST-TU Lisbon, Rua Alves Redol, 9, 1000-029, Portugal"],"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, ISEL-PI Lisbon, Technical University of Lisbon, IST, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]},{"raw_affiliation_string":"INESC-ID Lisbon, ISEL-PI Lisbon, IST-TU Lisbon, Rua Alves Redol, 9, 1000-029, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015710714","display_name":"Nuno Roma","orcid":"https://orcid.org/0000-0003-2491-4977"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Nuno Roma","raw_affiliation_strings":["INESC-ID Lisbon, ISEL-PI Lisbon, Technical University of Lisbon, IST, Lisboa, Portugal","INESC-ID Lisbon, ISEL-PI Lisbon, IST-TU Lisbon, Rua Alves Redol, 9, 1000-029, Portugal"],"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, ISEL-PI Lisbon, Technical University of Lisbon, IST, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]},{"raw_affiliation_string":"INESC-ID Lisbon, ISEL-PI Lisbon, IST-TU Lisbon, Rua Alves Redol, 9, 1000-029, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077537777","display_name":"Leonel Sousa","orcid":"https://orcid.org/0000-0002-8066-221X"},"institutions":[{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Leonel Sousa","raw_affiliation_strings":["INESC-ID Lisbon, ISEL-PI Lisbon, Technical University of Lisbon, IST, Lisboa, Portugal","INESC-ID Lisbon, ISEL-PI Lisbon, IST-TU Lisbon, Rua Alves Redol, 9, 1000-029, Portugal"],"affiliations":[{"raw_affiliation_string":"INESC-ID Lisbon, ISEL-PI Lisbon, Technical University of Lisbon, IST, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]},{"raw_affiliation_string":"INESC-ID Lisbon, ISEL-PI Lisbon, IST-TU Lisbon, Rua Alves Redol, 9, 1000-029, Portugal","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5091017679"],"corresponding_institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"],"apc_list":null,"apc_paid":null,"fwci":1.0145,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.77772133,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"242","last_page":"249"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12720","display_name":"Multimedia Communication and Technology","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/3312","display_name":"Sociology and Political Science"},"field":{"id":"https://openalex.org/fields/33","display_name":"Social Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},{"id":"https://openalex.org/T11165","display_name":"Image and Video Quality Assessment","score":0.9894000291824341,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.8136544823646545},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8024128675460815},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.671276330947876},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6547410488128662},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6103899478912354},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.6060875654220581},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5481047630310059},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5452289581298828},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.44244641065597534},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.42631927132606506},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4155900776386261},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40772944688796997},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2174614667892456},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14539551734924316}],"concepts":[{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.8136544823646545},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8024128675460815},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.671276330947876},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6547410488128662},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6103899478912354},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.6060875654220581},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5481047630310059},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5452289581298828},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.44244641065597534},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.42631927132606506},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4155900776386261},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40772944688796997},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2174614667892456},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14539551734924316},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dasip.2010.5706271","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2010.5706271","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","raw_type":"proceedings-article"},{"id":"pmh:oai:repositorio.ipl.pt:10400.21/12300","is_oa":true,"landing_page_url":"http://hdl.handle.net/10400.21/12300","pdf_url":null,"source":{"id":"https://openalex.org/S4306400762","display_name":"Reposit\u00f3rio Cient\u00edfico do Instituto Polit\u00e9cnico de Lisboa (Instituto Polit\u00e9cnico de Lisboa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I203847022","host_organization_name":"Instituto Polit\u00e9cnico de Lisboa","host_organization_lineage":["https://openalex.org/I203847022"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference object"}],"best_oa_location":{"id":"pmh:oai:repositorio.ipl.pt:10400.21/12300","is_oa":true,"landing_page_url":"http://hdl.handle.net/10400.21/12300","pdf_url":null,"source":{"id":"https://openalex.org/S4306400762","display_name":"Reposit\u00f3rio Cient\u00edfico do Instituto Polit\u00e9cnico de Lisboa (Instituto Polit\u00e9cnico de Lisboa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I203847022","host_organization_name":"Instituto Polit\u00e9cnico de Lisboa","host_organization_lineage":["https://openalex.org/I203847022"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference object"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1989533044","https://openalex.org/W2109271986","https://openalex.org/W2110448566","https://openalex.org/W2121840029","https://openalex.org/W2139774295","https://openalex.org/W2533368764"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2027972911","https://openalex.org/W3012895752","https://openalex.org/W2025467172","https://openalex.org/W2532502681"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,38,66,93,106,129],"multi-core":[4],"H.264/AVC":[5,98],"encoder":[6,29,99],"suitable":[7],"for":[8],"implementations":[9],"in":[10,37,92],"small":[11],"and":[12,35,41,51,68,78],"medium":[13],"complexity":[14],"embedded":[15],"systems.":[16],"The":[17,62],"proposed":[18],"structure":[19],"results":[20,87],"from":[21],"an":[22,97,101],"efficient":[23,42,69],"hardware/software":[24],"co-design":[25],"methodology,":[26],"where":[27],"the":[28,76,79,90,112,118,134],"software":[30],"application":[31],"is":[32],"highly":[33],"optimized":[34,83],"structured":[36],"very":[39,130],"modular":[40],"manner,":[43],"so":[44],"as":[45,105],"to":[46,55,58,73],"allow":[47,75],"its":[48],"most":[49],"complex":[50],"time":[52],"consuming":[53],"operations":[54],"be":[56],"offloaded":[57],"dedicated":[59],"hardware":[60,108,136],"accelerators.":[61],"considered":[63,119],"methodology":[64],"adopts":[65],"simple":[67],"core":[70,104],"interconnection":[71],"mechanism":[72],"easily":[74],"inclusion":[77],"removal":[80],"of":[81,96,114,133],"such":[82],"processing":[84],"cores.":[85],"Experimental":[86],"obtained":[88,127],"with":[89,128],"implementation":[91],"Virtex4":[94],"FPGA":[95],"using":[100],"ASIP":[102],"IP":[103],"ME":[107],"accelerator":[109],"have":[110],"proven":[111],"advantages":[113],"this":[115],"methodology.":[116],"For":[117],"system,":[120],"speedup":[121],"factors":[122],"greater":[123],"than":[124],"15":[125],"were":[126],"modest":[131],"increase":[132],"involved":[135],"resources.":[137]},"counts_by_year":[{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
