{"id":"https://openalex.org/W2134012933","doi":"https://doi.org/10.1109/dasip.2010.5706241","title":"High speed F&lt;inf&gt;p&lt;/inf&gt; multipliers and adders on FPGA platform","display_name":"High speed F&lt;inf&gt;p&lt;/inf&gt; multipliers and adders on FPGA platform","publication_year":2010,"publication_date":"2010-10-01","ids":{"openalex":"https://openalex.org/W2134012933","doi":"https://doi.org/10.1109/dasip.2010.5706241","mag":"2134012933"},"language":"en","primary_location":{"id":"doi:10.1109/dasip.2010.5706241","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2010.5706241","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051982414","display_name":"Santosh K. Ghosh","orcid":"https://orcid.org/0000-0001-5669-7853"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Santosh Ghosh","raw_affiliation_strings":["Department of Computer Science & Engineering, Indian Institute of Technology, Kharagpur, West Bengal, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science & Engineering, Indian Institute of Technology, Kharagpur, West Bengal, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078971402","display_name":"Debdeep Mukhopadhyay","orcid":"https://orcid.org/0000-0002-6499-8346"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Debdeep Mukhopadhyay","raw_affiliation_strings":["Department of Computer Science & Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science & Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109433484","display_name":"Dipanwita Roy Chowdhury","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Dipanwita Roy Chowdhury","raw_affiliation_strings":["Department of Computer Science & Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science & Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5051982414"],"corresponding_institution_ids":["https://openalex.org/I145894827"],"apc_list":null,"apc_paid":null,"fwci":2.0811,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.91279386,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"21","last_page":"26"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9090808629989624},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.816303014755249},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.794558584690094},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7540099620819092},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6087548732757568},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5445864200592041},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.505872905254364},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4782637357711792},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29750603437423706},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.24653515219688416},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24438819289207458},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13934075832366943},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12388554215431213},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0782599151134491}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9090808629989624},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.816303014755249},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.794558584690094},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7540099620819092},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6087548732757568},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5445864200592041},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.505872905254364},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4782637357711792},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29750603437423706},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.24653515219688416},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24438819289207458},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13934075832366943},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12388554215431213},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0782599151134491},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dasip.2010.5706241","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dasip.2010.5706241","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W158480116","https://openalex.org/W1893601685","https://openalex.org/W1972014440","https://openalex.org/W1981998307","https://openalex.org/W1995503477","https://openalex.org/W2004814164","https://openalex.org/W2023113280","https://openalex.org/W2063884927","https://openalex.org/W2073022907","https://openalex.org/W2096133993","https://openalex.org/W2097848615","https://openalex.org/W2110122313","https://openalex.org/W2110474813","https://openalex.org/W2113287980","https://openalex.org/W2117493063","https://openalex.org/W2121637803","https://openalex.org/W2134829359","https://openalex.org/W2135477346","https://openalex.org/W2144004675","https://openalex.org/W2149087966","https://openalex.org/W2153253155","https://openalex.org/W2157014293","https://openalex.org/W2161198480","https://openalex.org/W2168543008","https://openalex.org/W4237773356","https://openalex.org/W6649550151","https://openalex.org/W6674513603"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2027972911","https://openalex.org/W2146343568","https://openalex.org/W2013643406","https://openalex.org/W2157978810","https://openalex.org/W2597809628","https://openalex.org/W1886625815"],"abstract_inverted_index":{"The":[0,17,63],"paper":[1,44],"proposes":[2],"high":[3,54],"speed":[4,55],"FPGA":[5],"implementations":[6],"of":[7],"adders":[8],"and":[9,52],"multipliers":[10],"in":[11,30],"F":[12],"<sub":[13],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[14],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">p</sub>":[15],".":[16],"work":[18],"shows":[19,65],"through":[20],"experimental":[21],"results":[22],"that":[23,66],"due":[24],"to":[25],"optimized":[26],"addition":[27],"chain":[28],"available":[29],"such":[31],"devices,":[32],"Karatsuba":[33],"decomposition":[34],"upto":[35],"a":[36],"particular":[37],"level":[38],"improves":[39],"the":[40,43,53,67,74],"performance.":[41],"Further":[42],"modifies":[45],"existing":[46],"interleaved":[47],"multiplier":[48],"using":[49],"Montgomery":[50],"ladder":[51],"adder":[56],"circuits.":[57],"Extensive":[58],"experiments":[59],"have":[60],"been":[61],"performed.":[62],"result":[64],"proposed":[68],"design":[69],"provides":[70],"70%":[71],"speedup":[72],"from":[73],"best":[75],"known":[76],"designs.":[77]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
