{"id":"https://openalex.org/W4414197134","doi":"https://doi.org/10.1109/dac63849.2025.11133279","title":"AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs","display_name":"AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W4414197134","doi":"https://doi.org/10.1109/dac63849.2025.11133279"},"language":"en","primary_location":{"id":"doi:10.1109/dac63849.2025.11133279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11133279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102730198","display_name":"Jiawei Liang","orcid":"https://orcid.org/0000-0002-1338-7983"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Jiawei Liang","raw_affiliation_strings":["The Hong Kong University of Science and Technology"],"affiliations":[{"raw_affiliation_string":"The Hong Kong University of Science and Technology","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100716825","display_name":"Linfeng Du","orcid":"https://orcid.org/0000-0002-3007-4890"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Linfeng Du","raw_affiliation_strings":["The Hong Kong University of Science and Technology"],"affiliations":[{"raw_affiliation_string":"The Hong Kong University of Science and Technology","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102313358","display_name":"Xiaofeng Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Xiaofeng Zhou","raw_affiliation_strings":["The Hong Kong University of Science and Technology"],"affiliations":[{"raw_affiliation_string":"The Hong Kong University of Science and Technology","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101564905","display_name":"Zhe Lin","orcid":"https://orcid.org/0009-0002-1594-2335"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhe Lin","raw_affiliation_strings":["Sun Yat-sen University"],"affiliations":[{"raw_affiliation_string":"Sun Yat-sen University","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013248987","display_name":"Jiang Xu","orcid":"https://orcid.org/0000-0001-9089-7752"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jiang Xu","raw_affiliation_strings":["The Hong Kong University of Science and Technology (GZ)"],"affiliations":[{"raw_affiliation_string":"The Hong Kong University of Science and Technology (GZ)","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100441533","display_name":"Wei Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Wei Zhang","raw_affiliation_strings":["The Hong Kong University of Science and Technology"],"affiliations":[{"raw_affiliation_string":"The Hong Kong University of Science and Technology","institution_ids":["https://openalex.org/I200769079"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5102730198"],"corresponding_institution_ids":["https://openalex.org/I200769079"],"apc_list":null,"apc_paid":null,"fwci":0.8194,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.78781659,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7886999845504761},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7645000219345093},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6875},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5371000170707703},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5182999968528748},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5141000151634216},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.49549999833106995},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4684999883174896},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.4180999994277954},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.35920000076293945}],"concepts":[{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7886999845504761},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7645000219345093},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6875},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6473000049591064},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6273000240325928},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5371000170707703},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5182999968528748},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5141000151634216},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.49549999833106995},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4684999883174896},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.4180999994277954},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40209999680519104},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.35920000076293945},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.35679998993873596},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.3549000024795532},{"id":"https://openalex.org/C60798267","wikidata":"https://www.wikidata.org/wiki/Q1226939","display_name":"Division (mathematics)","level":2,"score":0.35269999504089355},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.3481000065803528},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.34389999508857727},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.336899995803833},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.3287999927997589},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.32510000467300415},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.3237000107765198},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.30480000376701355},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.30300000309944153},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.30239999294281006},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.29120001196861267},{"id":"https://openalex.org/C2778426721","wikidata":"https://www.wikidata.org/wiki/Q1225105","display_name":"Digital clock","level":3,"score":0.27559998631477356},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.26930001378059387},{"id":"https://openalex.org/C50661577","wikidata":"https://www.wikidata.org/wiki/Q901831","display_name":"Time-division multiplexing","level":3,"score":0.2653999924659729},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.25859999656677246},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.257099986076355}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac63849.2025.11133279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11133279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W2135374417","https://openalex.org/W2139356211","https://openalex.org/W2485163885","https://openalex.org/W2788211964","https://openalex.org/W2889995311","https://openalex.org/W2907573123","https://openalex.org/W2998625809","https://openalex.org/W3120734250","https://openalex.org/W3130920634","https://openalex.org/W3196072617","https://openalex.org/W3216619612","https://openalex.org/W4210258659","https://openalex.org/W4220772296","https://openalex.org/W4315588165","https://openalex.org/W4383749486","https://openalex.org/W4386710216","https://openalex.org/W4389166651","https://openalex.org/W4400232127"],"related_works":[],"abstract_inverted_index":{"High-level":[0],"synthesis":[1],"(HLS)":[2],"tools":[3,44],"streamline":[4],"FPGA":[5,29],"design":[6,60],"by":[7,118,150],"enabling":[8],"engineers":[9],"to":[10,105,152],"implement":[11],"hardware":[12],"using":[13],"$\\mathrm{C}":[14],"/":[15],"\\mathrm{C}++$":[16],"languages.":[17],"However,":[18],"while":[19],"clock":[20,49,55,73,89,101,107,126,140],"management":[21,90],"serves":[22],"as":[23],"a":[24,58,130],"critical":[25],"stage":[26],"in":[27,80,129],"the":[28,52,64,68,125],"EDA":[30],"flow":[31],"that":[32,92,135],"affects":[33],"system-level":[34],"performance,":[35],"area,":[36],"and":[37,67,111,122,144],"especially":[38],"power":[39,148],"consumption,":[40],"existing":[41],"commercial":[42],"HLS":[43],"lack":[45],"comprehensive":[46],"solutions":[47],"for":[48,62,100],"management.":[50],"Specifically,":[51],"diversity":[53],"of":[54,71,127],"resources":[56,99,141],"creates":[57],"vast":[59],"space":[61],"finding":[63],"optimal":[65],"configuration,":[66],"insufficient":[69],"analysis":[70],"multiple":[72],"domain":[74,120],"scenarios":[75],"hinders":[76],"effective":[77],"clock-oriented":[78],"optimizations":[79],"HLS.":[81,96],"This":[82],"work":[83],"introduces":[84],"AutoClock,":[85],"an":[86],"open-source":[87],"integrated":[88],"framework":[91],"complements":[93],"AMD":[94],"Vitis":[95],"AutoClock":[97,136],"allocates":[98],"generation,":[102],"assigns":[103],"modules":[104,128],"appropriate":[106],"domains,":[108],"addresses":[109],"metastability":[110],"time":[112],"division":[113],"multiplexing":[114],"(TDM)":[115],"malfunctioning":[116],"introduced":[117],"multiclock":[119],"architectures,":[121],"hierarchically":[123],"gates":[124],"design.":[131],"Experimental":[132],"results":[133],"demonstrate":[134],"can":[137],"fully":[138],"utilize":[139],"on":[142],"FPGAs":[143],"help":[145],"reduce":[146],"dynamic":[147],"consumption":[149],"up":[151],"74.38%.":[153]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-10-10T00:00:00"}