{"id":"https://openalex.org/W4414197367","doi":"https://doi.org/10.1109/dac63849.2025.11133110","title":"E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis","display_name":"E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W4414197367","doi":"https://doi.org/10.1109/dac63849.2025.11133110"},"language":"en","primary_location":{"id":"doi:10.1109/dac63849.2025.11133110","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11133110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111892447","display_name":"Chen Chen","orcid":"https://orcid.org/0009-0007-8825-6260"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Chen Chen","raw_affiliation_strings":["HKUST(GZ)"],"affiliations":[{"raw_affiliation_string":"HKUST(GZ)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080163434","display_name":"Guangyu Hu","orcid":"https://orcid.org/0000-0001-5077-8361"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Guangyu Hu","raw_affiliation_strings":["HKUST"],"affiliations":[{"raw_affiliation_string":"HKUST","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029321729","display_name":"Cunxi Yu","orcid":"https://orcid.org/0000-0003-3481-307X"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cunxi Yu","raw_affiliation_strings":["University of Maryland,College Park"],"affiliations":[{"raw_affiliation_string":"University of Maryland,College Park","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071995111","display_name":"Yuzhe Ma","orcid":"https://orcid.org/0000-0002-3612-4182"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yuzhe Ma","raw_affiliation_strings":["HKUST(GZ)"],"affiliations":[{"raw_affiliation_string":"HKUST(GZ)","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003614499","display_name":"Hongce Zhang","orcid":"https://orcid.org/0000-0003-4001-264X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hongce Zhang","raw_affiliation_strings":["HKUST(GZ)"],"affiliations":[{"raw_affiliation_string":"HKUST(GZ)","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5111892447"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":8.7931,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.97819797,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9244999885559082,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9244999885559082,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.921500027179718,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9114999771118164,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7721999883651733},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5770999789237976},{"id":"https://openalex.org/keywords/rewriting","display_name":"Rewriting","score":0.565500020980835},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5135999917984009},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.483599990606308},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.38530001044273376},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3758000135421753},{"id":"https://openalex.org/keywords/saturation","display_name":"Saturation (graph theory)","score":0.375}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7721999883651733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5845000147819519},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5770999789237976},{"id":"https://openalex.org/C154690210","wikidata":"https://www.wikidata.org/wiki/Q1668499","display_name":"Rewriting","level":2,"score":0.565500020980835},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5135999917984009},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.483599990606308},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.38530001044273376},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.375900000333786},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3758000135421753},{"id":"https://openalex.org/C9930424","wikidata":"https://www.wikidata.org/wiki/Q7426587","display_name":"Saturation (graph theory)","level":2,"score":0.375},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.365200012922287},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33090001344680786},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.319599986076355},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.3052000105381012},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3041999936103821},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.2985999882221222},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.29600000381469727},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.29580000042915344},{"id":"https://openalex.org/C108710211","wikidata":"https://www.wikidata.org/wiki/Q11538","display_name":"Mathematical proof","level":2,"score":0.2870999872684479},{"id":"https://openalex.org/C3018263672","wikidata":"https://www.wikidata.org/wiki/Q1296251","display_name":"Efficient algorithm","level":2,"score":0.27810001373291016},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.27799999713897705},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2761000096797943},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.26170000433921814},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2554999887943268},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.25189998745918274}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dac63849.2025.11133110","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11133110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-166435","is_oa":false,"landing_page_url":"http://repository.hkust.edu.hk/ir/Record/1783.1-166435","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320335480","display_name":"Guangzhou Municipal Science and Technology Project","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2024060531","https://openalex.org/W2100465945","https://openalex.org/W2129147175","https://openalex.org/W2346205343","https://openalex.org/W3099525000","https://openalex.org/W3145367831","https://openalex.org/W4230919050","https://openalex.org/W4239323126","https://openalex.org/W4240866746","https://openalex.org/W4246264663","https://openalex.org/W4249982533","https://openalex.org/W4256548512","https://openalex.org/W4282032146","https://openalex.org/W4312288277","https://openalex.org/W4378801004","https://openalex.org/W4386763476","https://openalex.org/W4386763903","https://openalex.org/W4393380051","https://openalex.org/W4404133761","https://openalex.org/W4404134032"],"related_works":[],"abstract_inverted_index":{"In":[0],"technology":[1,73],"mapping,":[2],"the":[3,6,12,55,81,103,114,135,154,158],"quality":[4],"of":[5,108],"final":[7],"implementation":[8],"heavily":[9],"relies":[10],"on":[11,143,153],"circuit":[13],"structure":[14,70],"after":[15,64],"technologyindependent":[16],"optimization.":[17],"Recent":[18],"studies":[19],"have":[20],"introduced":[21],"equality":[22,60,82],"saturation":[23,61,83],"as":[24,86],"a":[25,33,45],"novel":[26],"optimization":[27,138],"approach.":[28],"However,":[29],"its":[30,36],"efficiency":[31,107],"remains":[32],"hurdle":[34],"against":[35],"wide":[37],"adoption":[38],"in":[39,119,140,157],"logic":[40,67,121],"synthesis.":[41],"This":[42],"paper":[43],"proposes":[44],"highly":[46],"scalable":[47],"and":[48,92,105,128,149],"efficient":[49],"framework":[50],"named":[51],"E-morphic.":[52],"It":[53],"is":[54],"first":[56],"work":[57],"that":[58],"employs":[59],"for":[62,95],"resynthesis":[63],"conventional":[65,120],"technology-independent":[66],"optimizations,":[68],"enabling":[69],"exploration":[71,127],"before":[72],"mapping.":[74],"Powered":[75],"by":[76],"several":[77],"key":[78],"enhancements":[79],"to":[80,134],"framework,":[84],"such":[85],"direct":[87],"e-graph-circuit":[88],"conversion,":[89],"solution-space":[90],"pruning,":[91],"simulated":[93],"annealing":[94],"e-graph":[96,109],"extraction,":[97],"this":[98],"approach":[99],"not":[100],"only":[101],"improves":[102],"scalability":[104],"extraction":[106],"rewriting":[110],"but":[111],"also":[112],"addresses":[113],"structural":[115,126],"bias":[116],"issue":[117],"present":[118],"synthesis":[122],"flows":[123],"through":[124],"parallel":[125],"resynthesis.":[129],"Experiments":[130],"show":[131],"that,":[132],"compared":[133],"state-of-the-art":[136],"delay":[137,151],"flow":[139],"ABC,":[141],"E-morphic":[142],"average":[144],"achieves":[145],"12.54%":[146],"area":[147],"saving":[148],"7.29%":[150],"reduction":[152],"large-scale":[155],"circuits":[156],"EPFL":[159],"benchmark.":[160]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3}],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}
