{"id":"https://openalex.org/W4414197736","doi":"https://doi.org/10.1109/dac63849.2025.11132888","title":"Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs","display_name":"Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W4414197736","doi":"https://doi.org/10.1109/dac63849.2025.11132888"},"language":"en","primary_location":{"id":"doi:10.1109/dac63849.2025.11132888","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132888","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100394256","display_name":"Yao Chen","orcid":"https://orcid.org/0000-0002-5798-2282"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Yao Chen","raw_affiliation_strings":["National University of Singapore,Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National University of Singapore,Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103764451","display_name":"Feng Yu","orcid":"https://orcid.org/0009-0000-0757-0469"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Feng Yu","raw_affiliation_strings":["National University of Singapore,Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National University of Singapore,Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033050983","display_name":"Di Wu","orcid":"https://orcid.org/0000-0003-1096-7074"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Di Wu","raw_affiliation_strings":["University of Science and Technology of China,Hefei,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Science and Technology of China,Hefei,China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023989495","display_name":"Weng\u2010Fai Wong","orcid":"https://orcid.org/0000-0002-4281-2053"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Weng-Fai Wong","raw_affiliation_strings":["National University of Singapore,Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National University of Singapore,Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039946576","display_name":"Bingsheng He","orcid":"https://orcid.org/0000-0001-8618-4581"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Bingsheng He","raw_affiliation_strings":["National University of Singapore,Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National University of Singapore,Singapore","institution_ids":["https://openalex.org/I165932596"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9886000156402588,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9886000156402588,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9726999998092651,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9702000021934509,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7190999984741211},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5412999987602234},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5394999980926514},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.49480000138282776},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.3986999988555908},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.3935000002384186},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.3709999918937683},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.3659000098705292}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7353000044822693},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7190999984741211},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6290000081062317},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5928000211715698},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5412999987602234},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5394999980926514},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.49480000138282776},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40880000591278076},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.3986999988555908},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.3935000002384186},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.3709999918937683},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.3659000098705292},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.36550000309944153},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.3626999855041504},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3043999969959259},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.29109999537467957},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.2802000045776367},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.27799999713897705},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.27790001034736633},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2750999927520752},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.2685999870300293},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.2628999948501587},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.26170000433921814}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac63849.2025.11132888","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132888","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2561621772","https://openalex.org/W2587748659","https://openalex.org/W2760769382","https://openalex.org/W2795975079","https://openalex.org/W2933246250","https://openalex.org/W2947178375","https://openalex.org/W2953082982","https://openalex.org/W3091884602","https://openalex.org/W3213694280","https://openalex.org/W4239721110","https://openalex.org/W4379116000"],"related_works":[],"abstract_inverted_index":{"Content-addressable":[0],"memory":[1,8,26],"(CAM)":[2],"is":[3,238],"a":[4,129,211],"type":[5],"of":[6,17,54,83,98,119,205,221],"fast":[7],"unique":[9],"in":[10,32,143],"its":[11],"ability":[12],"to":[13,79,111,193],"perform":[14],"parallel":[15,104],"searches":[16],"stored":[18],"data":[19,154],"based":[20],"on":[21,215,233],"content":[22],"rather":[23],"than":[24],"specific":[25],"addresses.":[27],"They":[28],"have":[29],"been":[30],"used":[31],"many":[33],"domains,":[34],"such":[35,63],"as":[36,146],"networking,":[37],"databases,":[38],"and":[39,59,75,87,156,173,189,196],"graph":[40],"processing.":[41],"Field-programmable":[42],"gate":[43],"arrays":[44],"(FPGAs)":[45],"are":[46],"an":[47],"attractive":[48],"platform":[49],"for":[50,176,229],"implementing":[51],"CAMs":[52],"because":[53],"their":[55],"low":[56],"latency,":[57],"reconfigurability,":[58],"energy-efficient":[60],"nature.":[61],"However,":[62],"implementations":[64],"also":[65,224],"face":[66],"significant":[67],"challenges,":[68,126],"including":[69],"high":[70],"resource":[71],"utilization,":[72],"limited":[73],"scalability,":[74,185],"suboptimal":[76],"performance":[77,191],"due":[78],"the":[80,95,103,117,136,147,203],"extensive":[81],"use":[82,220],"look-up":[84],"tables":[85],"(LUTs)":[86],"block":[88],"RAMs":[89],"(BRAMs).":[90],"These":[91],"issues":[92],"stem":[93],"from":[94],"inherent":[96],"limitations":[97],"FPGA":[99],"architectures":[100],"when":[101],"handling":[102],"operations":[105],"required":[106],"by":[107],"CAMs,":[108],"often":[109],"leading":[110],"inefficient":[112],"designs":[113],"that":[114,134],"cannot":[115],"meet":[116],"demands":[118],"high-speed,":[120],"data-intensive":[121,177,231],"applications.":[122,178],"To":[123],"address":[124],"these":[125],"we":[127,201],"propose":[128],"novel":[130],"configurable":[131,162],"CAM":[132,163,181,208],"architecture":[133,164,182,209],"leverages":[135],"digital":[137],"signal":[138],"processing":[139],"(DSP)":[140],"blocks":[141,223],"available":[142],"modern":[144],"FPGAs":[145],"core":[148],"resource.":[149],"By":[150],"utilizing":[151],"DSP":[152,222],"blocks\u2019":[153],"storage":[155],"logic":[157],"capabilities,":[158],"our":[159,206],"approach":[160],"enables":[161],"with":[165,210],"efficient":[166],"multi-query":[167],"support":[168],"while":[169],"significantly":[170],"reducing":[171],"search":[172],"update":[174],"latency":[175],"The":[179],"DSP-based":[180],"offers":[183],"enhanced":[184],"higher":[186],"operating":[187],"frequency,":[188],"improved":[190],"compared":[192],"traditional":[194],"LUT":[195],"BRAM-based":[197],"designs.":[198],"In":[199],"addition,":[200],"demonstrate":[202],"effectiveness":[204],"proposed":[207,236],"triangle":[212],"counting":[213],"application":[214],"real":[216],"graphs.":[217],"This":[218],"innovative":[219],"opens":[225],"up":[226],"new":[227],"possibilities":[228],"highperformance,":[230],"applications":[232],"FPGAs.":[234],"Our":[235],"design":[237],"open-sourced":[239],"at:":[240],"https://github.com/Xtra-Computing/DSP_CAM/.":[241]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
