{"id":"https://openalex.org/W4414197463","doi":"https://doi.org/10.1109/dac63849.2025.11132615","title":"Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories","display_name":"Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W4414197463","doi":"https://doi.org/10.1109/dac63849.2025.11132615"},"language":"en","primary_location":{"id":"doi:10.1109/dac63849.2025.11132615","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132615","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047845757","display_name":"Faaiq Waqar","orcid":"https://orcid.org/0009-0008-1005-6098"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Faaiq Waqar","raw_affiliation_strings":["Georgia Institute of Technology,Atlanta,GA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology,Atlanta,GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101463934","display_name":"Jiahao Zhang","orcid":"https://orcid.org/0009-0005-1993-8132"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiahao Zhang","raw_affiliation_strings":["University of California – Los Angeles,Los Angeles,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California – Los Angeles,Los Angeles,CA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072117537","display_name":"Anni Lu","orcid":"https://orcid.org/0000-0002-4415-0866"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anni Lu","raw_affiliation_strings":["Georgia Institute of Technology,Atlanta,GA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology,Atlanta,GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103241031","display_name":"Zifan He","orcid":"https://orcid.org/0009-0008-3482-838X"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zifan He","raw_affiliation_strings":["University of California – Los Angeles,Los Angeles,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California – Los Angeles,Los Angeles,CA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016776689","display_name":"Jason Cong","orcid":"https://orcid.org/0000-0003-2887-6963"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Cong","raw_affiliation_strings":["University of California – Los Angeles,Los Angeles,CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California – Los Angeles,Los Angeles,CA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054894631","display_name":"Shimeng Yu","orcid":"https://orcid.org/0000-0002-0068-3652"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shimeng Yu","raw_affiliation_strings":["Georgia Institute of Technology,Atlanta,GA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology,Atlanta,GA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.0301,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.91017488,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9930999875068665,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9828000068664551,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.6703000068664551},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.613099992275238},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.6008999943733215},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5457000136375427},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5145000219345093},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4934000074863434},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.48429998755455017},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.430400013923645},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.42669999599456787},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.42649999260902405}],"concepts":[{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.6703000068664551},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.613099992275238},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.6008999943733215},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5612999796867371},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5457000136375427},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5145000219345093},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4934000074863434},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.48429998755455017},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48030000925064087},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.430400013923645},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.42669999599456787},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.42649999260902405},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.41600000858306885},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4088999927043915},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4009999930858612},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.39750000834465027},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.38600000739097595},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.37549999356269836},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.37299999594688416},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.3725000023841858},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.349700003862381},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.33899998664855957},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3165999948978424},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.31470000743865967},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.30070000886917114},{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.29510000348091125},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.29170000553131104},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.2865999937057495},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.28450000286102295},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.27709999680519104},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.2669999897480011},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.25679999589920044},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2558000087738037}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac63849.2025.11132615","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132615","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1966460368","https://openalex.org/W1976834654","https://openalex.org/W1977773606","https://openalex.org/W1982968328","https://openalex.org/W2024413189","https://openalex.org/W2074599790","https://openalex.org/W2085743209","https://openalex.org/W2086709250","https://openalex.org/W2117493063","https://openalex.org/W2118443094","https://openalex.org/W2120544688","https://openalex.org/W2782046614","https://openalex.org/W2895540242","https://openalex.org/W2898878850","https://openalex.org/W2911751195","https://openalex.org/W3013082411","https://openalex.org/W3033033241","https://openalex.org/W3092005229","https://openalex.org/W3137059735","https://openalex.org/W3147376636","https://openalex.org/W3147395157","https://openalex.org/W3147788730","https://openalex.org/W3162937989","https://openalex.org/W3166559827","https://openalex.org/W4211147898","https://openalex.org/W4212902471","https://openalex.org/W4285111918","https://openalex.org/W4381050415","https://openalex.org/W4394896788","https://openalex.org/W4398774985","https://openalex.org/W4401717600","https://openalex.org/W4401879621","https://openalex.org/W4401880215","https://openalex.org/W4401881133","https://openalex.org/W4403759393","https://openalex.org/W4403938131"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,54],"novel":[4],"monolithic":[5],"3D":[6],"(M3D)":[7],"FPGA":[8,115,150],"architecture":[9],"that":[10,58,97],"leverages":[11],"stackable":[12],"back-end-of-line":[13],"(BEOL)":[14],"transistors":[15,43,67],"to":[16,90],"implement":[17],"configuration":[18,49],"memory":[19],"and":[20,27,36,73,119,136,172,184],"pass":[21,105],"gates,":[22],"significantly":[23],"improving":[24],"area,":[25],"latency,":[26,171],"power":[28,178],"efficiency.":[29],"By":[30,139],"integrating":[31],"n-type":[32],"(W":[33],"-doped":[34],"In2O3)":[35],"p-type":[37],"(SnO)":[38],"amorphous":[39],"oxide":[40],"semiconductor":[41],"(AOS)":[42],"in":[44,75,95,152],"the":[45,76,108,131,142],"BEOL,":[46],"Si":[47],"SRAM":[48],"bits":[50],"are":[51,68],"substituted":[52],"with":[53,79,141,158],"less":[55],"leaky":[56],"equivalent":[57],"can":[59],"be":[60],"programmed":[61],"at":[62],"logic-compatible":[63],"voltages.":[64],"BEOL-compatible":[65],"AOS":[66,104],"currently":[69],"under":[70],"extensive":[71],"research":[72],"development":[74],"device":[77],"community,":[78],"investment":[80],"by":[81,113],"leading":[82],"foundries,":[83],"from":[84],"which":[85],"reported":[86],"data":[87],"is":[88,156],"used":[89],"develop":[91],"robust":[92],"physics-based":[93],"models":[94,187],"TCAD":[96],"enable":[98],"circuit":[99],"design.":[100],"The":[101],"use":[102],"of":[103,110,133],"gates":[106],"reduces":[107],"overhead":[109],"reconfigurable":[111,175],"circuits":[112],"mapping":[114],"switch":[116],"block":[117,121,177],"(SB)":[118],"connection":[120],"(CB)":[122],"matrices":[123],"above":[124],"configurable":[125],"logic":[126,134],"blocks":[127],"(CLBs),":[128],"thereby":[129],"increasing":[130],"proximity":[132],"elements":[135],"reducing":[137],"latency.":[138],"interfacing":[140],"latest":[143],"Verilog-to-Routing":[144],"(VTR)":[145],"suite,":[146],"an":[147],"AOS-based":[148],"M3D":[149],"implemented":[151],"7":[153],"nm":[154],"technology":[155],"demonstrated":[157],"$3.4":[159],"\\times$":[160],"lower":[161,168,174],"area-time":[162],"squared":[163],"product":[164],"($\\mathbf{A":[165],"T}^{2}$),":[166],"27%":[167],"critical":[169],"path":[170],"26%":[173],"routing":[176],"on":[179],"benchmarks":[180],"including":[181],"hyperdimensional":[182],"computing":[183],"large":[185],"language":[186],"(LLMs).":[188]},"counts_by_year":[{"year":2026,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}