{"id":"https://openalex.org/W4414197180","doi":"https://doi.org/10.1109/dac63849.2025.11132598","title":"ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions","display_name":"ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W4414197180","doi":"https://doi.org/10.1109/dac63849.2025.11132598"},"language":"en","primary_location":{"id":"doi:10.1109/dac63849.2025.11132598","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132598","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5099073214","display_name":"Vincenzo Petrolo","orcid":"https://orcid.org/0009-0002-4923-7052"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Vincenzo Petrolo","raw_affiliation_strings":["VLSI Lab Politecnico di Torino,Italy"],"affiliations":[{"raw_affiliation_string":"VLSI Lab Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093679490","display_name":"Flavia Guella","orcid":"https://orcid.org/0009-0000-6725-0416"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Flavia Guella","raw_affiliation_strings":["VLSI Lab Politecnico di Torino,Italy"],"affiliations":[{"raw_affiliation_string":"VLSI Lab Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013253742","display_name":"Michele Caon","orcid":"https://orcid.org/0009-0009-4446-8389"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Michele Caon","raw_affiliation_strings":["VLSI Lab Politecnico di Torino,Italy"],"affiliations":[{"raw_affiliation_string":"VLSI Lab Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019754330","display_name":"Pasquale Davide Schiavone","orcid":"https://orcid.org/0000-0003-2931-0435"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]},{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Pasquale Davide Schiavone","raw_affiliation_strings":["Embedded Systems Laboratory EPFL,Switzerland"],"affiliations":[{"raw_affiliation_string":"Embedded Systems Laboratory EPFL,Switzerland","institution_ids":["https://openalex.org/I5124864","https://openalex.org/I4210145666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074150684","display_name":"Guido Masera","orcid":"https://orcid.org/0000-0003-2238-9443"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Guido Masera","raw_affiliation_strings":["VLSI Lab Politecnico di Torino,Italy"],"affiliations":[{"raw_affiliation_string":"VLSI Lab Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026016005","display_name":"Maurizio Martina","orcid":"https://orcid.org/0000-0002-3069-0319"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Maurizio Martina","raw_affiliation_strings":["VLSI Lab Politecnico di Torino,Italy"],"affiliations":[{"raw_affiliation_string":"VLSI Lab Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5099073214"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27865718,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.717199981212616},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5291000008583069},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.5242000222206116},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.4778999984264374},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.43389999866485596},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.3950999975204468},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.3682999908924103},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.34700000286102295},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3402000069618225},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.33500000834465027}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8579999804496765},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.717199981212616},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5291000008583069},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.5242000222206116},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4821999967098236},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.4778999984264374},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.44749999046325684},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.43389999866485596},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42730000615119934},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.3950999975204468},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.3682999908924103},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.34700000286102295},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3402000069618225},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.33500000834465027},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3310999870300293},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.3310000002384186},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.33070001006126404},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.3156000077724457},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.3149000108242035},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.30649998784065247},{"id":"https://openalex.org/C170130773","wikidata":"https://www.wikidata.org/wiki/Q216378","display_name":"Usability","level":2,"score":0.30390000343322754},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.30250000953674316},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.29350000619888306},{"id":"https://openalex.org/C59687516","wikidata":"https://www.wikidata.org/wiki/Q5015938","display_name":"Cache-oblivious algorithm","level":5,"score":0.289000004529953},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.2881999909877777},{"id":"https://openalex.org/C154240960","wikidata":"https://www.wikidata.org/wiki/Q2860294","display_name":"Database-centric architecture","level":5,"score":0.2824999988079071},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2766999900341034},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.275299996137619},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.2621000111103058},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.26190000772476196},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.25369998812675476},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.251800000667572}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac63849.2025.11132598","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132598","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2613569094","https://openalex.org/W2950138172","https://openalex.org/W2963255460","https://openalex.org/W3048581975","https://openalex.org/W3161571687","https://openalex.org/W3190854509","https://openalex.org/W4313192083","https://openalex.org/W4385585336","https://openalex.org/W4393145114"],"related_works":[],"abstract_inverted_index":{"Modern":[0],"data-driven":[1],"applications":[2],"expose":[3],"limitations":[4],"of":[5],"von":[6],"Neumann":[7],"architectures-extensive":[8],"data":[9,25,42,89,115],"movement,":[10],"low":[11],"throughput,":[12],"and":[13,23,30,88],"poor":[14],"energy":[15],"efficiency.":[16],"Accelerators":[17],"improve":[18],"performance":[19,109],"but":[20,36],"lack":[21],"flexibility":[22],"require":[24],"transfers.":[26],"Existing":[27],"compute":[28],"in-":[29],"nearmemory":[31],"solutions":[32],"mitigate":[33],"these":[34],"issues":[35],"face":[37],"usability":[38],"challenges":[39],"due":[40],"to":[41,73,106],"placement":[43],"constraints.":[44],"We":[45],"propose":[46],"a":[47,54,121,126],"novel":[48],"cache":[49,60,80,123],"architecture":[50,84],"that":[51],"doubles":[52],"as":[53],"tightly-coupled":[55],"compute-near-memory":[56],"coprocessor.":[57],"Our":[58,101],"RISC-V":[59],"controller":[61],"executes":[62],"custom":[63],"instructions":[64],"from":[65,91],"the":[66,79,117],"host":[67],"CPU":[68],"using":[69],"vector":[70,75],"operations":[71],"dispatched":[72],"near-memory":[74],"processing":[76],"units":[77],"within":[78],"memory":[81,86],"subsystem.":[82],"This":[83],"abstracts":[85],"synchronization":[87],"mapping":[90],"application":[92],"software":[93],"while":[94],"offering":[95],"software-based":[96],"Instruction":[97],"Set":[98],"Architecture":[99],"extensibility.":[100],"implementation":[102],"shows":[103],"$30":[104],"\\times$":[105,108],"$84":[107],"improvement":[110],"when":[111,124],"operating":[112],"on":[113],"8-bit":[114],"over":[116],"same":[118],"system":[119],"with":[120,131],"traditional":[122],"executing":[125],"worst-case":[127],"32-bit":[128],"CNN":[129],"workload,":[130],"only":[132],"41.3%":[133],"area":[134],"overhead.":[135]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-10-10T00:00:00"}