{"id":"https://openalex.org/W4414197486","doi":"https://doi.org/10.1109/dac63849.2025.11132483","title":"YAP: Yield Modeling and Simulation for Advanced Packaging","display_name":"YAP: Yield Modeling and Simulation for Advanced Packaging","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W4414197486","doi":"https://doi.org/10.1109/dac63849.2025.11132483"},"language":"en","primary_location":{"id":"doi:10.1109/dac63849.2025.11132483","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132483","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029303179","display_name":"Zhichao Chen","orcid":"https://orcid.org/0009-0003-0107-8512"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Zhichao Chen","raw_affiliation_strings":["University of California,Department of Electrical and Computer Engineering,Los Angeles"],"affiliations":[{"raw_affiliation_string":"University of California,Department of Electrical and Computer Engineering,Los Angeles","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084229134","display_name":"Puneet Gupta","orcid":"https://orcid.org/0000-0002-6188-1134"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Puneet Gupta","raw_affiliation_strings":["University of California,Department of Electrical and Computer Engineering,Los Angeles"],"affiliations":[{"raw_affiliation_string":"University of California,Department of Electrical and Computer Engineering,Los Angeles","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5029303179"],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27340265,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12971","display_name":"Material Properties and Processing","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2211","display_name":"Mechanics of Materials"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12971","display_name":"Material Properties and Processing","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2211","display_name":"Mechanics of Materials"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.9898999929428101,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.9750000238418579,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.7387999892234802},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6439999938011169},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5443000197410583},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.4747999906539917},{"id":"https://openalex.org/keywords/integrated-circuit-packaging","display_name":"Integrated circuit packaging","score":0.4722999930381775},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.4499000012874603},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.43299999833106995},{"id":"https://openalex.org/keywords/semiconductor-device-modeling","display_name":"Semiconductor device modeling","score":0.3898000121116638},{"id":"https://openalex.org/keywords/wire-bonding","display_name":"Wire bonding","score":0.34940001368522644},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.3427000045776367}],"concepts":[{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.7387999892234802},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6439999938011169},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5443000197410583},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.4747999906539917},{"id":"https://openalex.org/C186260285","wikidata":"https://www.wikidata.org/wiki/Q759494","display_name":"Integrated circuit packaging","level":3,"score":0.4722999930381775},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.4499000012874603},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.43299999833106995},{"id":"https://openalex.org/C4775677","wikidata":"https://www.wikidata.org/wiki/Q7449393","display_name":"Semiconductor device modeling","level":3,"score":0.3898000121116638},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3779999911785126},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3720000088214874},{"id":"https://openalex.org/C140269135","wikidata":"https://www.wikidata.org/wiki/Q750783","display_name":"Wire bonding","level":3,"score":0.34940001368522644},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3490999937057495},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.3427000045776367},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33640000224113464},{"id":"https://openalex.org/C54725748","wikidata":"https://www.wikidata.org/wiki/Q7247277","display_name":"Process integration","level":2,"score":0.3303999900817871},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.3303000032901764},{"id":"https://openalex.org/C21880701","wikidata":"https://www.wikidata.org/wiki/Q2144042","display_name":"Process engineering","level":1,"score":0.32910001277923584},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.3246000111103058},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.31790000200271606},{"id":"https://openalex.org/C167343916","wikidata":"https://www.wikidata.org/wiki/Q6888384","display_name":"Modeling and simulation","level":2,"score":0.31769999861717224},{"id":"https://openalex.org/C146667757","wikidata":"https://www.wikidata.org/wiki/Q1457198","display_name":"System in package","level":3,"score":0.30979999899864197},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.3075999915599823},{"id":"https://openalex.org/C2779133538","wikidata":"https://www.wikidata.org/wiki/Q677010","display_name":"Wafer bonding","level":3,"score":0.305400013923645},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.29820001125335693},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.29789999127388},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2955000102519989},{"id":"https://openalex.org/C108215451","wikidata":"https://www.wikidata.org/wiki/Q7263963","display_name":"Simulation modeling","level":2,"score":0.2897999882698059},{"id":"https://openalex.org/C69567186","wikidata":"https://www.wikidata.org/wiki/Q5358403","display_name":"Electronic packaging","level":2,"score":0.2800000011920929},{"id":"https://openalex.org/C2778517922","wikidata":"https://www.wikidata.org/wiki/Q7140482","display_name":"Particle (ecology)","level":2,"score":0.27390000224113464},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2646999955177307},{"id":"https://openalex.org/C55396564","wikidata":"https://www.wikidata.org/wiki/Q3084971","display_name":"Process design","level":3,"score":0.263700008392334},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.25859999656677246},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.2556999921798706},{"id":"https://openalex.org/C174998907","wikidata":"https://www.wikidata.org/wiki/Q357662","display_name":"Work in process","level":2,"score":0.25220000743865967},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.25119999051094055},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.25099998712539673}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac63849.2025.11132483","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac63849.2025.11132483","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 62nd ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1549923431","https://openalex.org/W1984450658","https://openalex.org/W1993815004","https://openalex.org/W2063772879","https://openalex.org/W2081793861","https://openalex.org/W2106780604","https://openalex.org/W2129555080","https://openalex.org/W2137602438","https://openalex.org/W2157220601","https://openalex.org/W2163527399","https://openalex.org/W2179061937","https://openalex.org/W2302246083","https://openalex.org/W2562062433","https://openalex.org/W2785863405","https://openalex.org/W3011687903","https://openalex.org/W3048129076","https://openalex.org/W3095571208","https://openalex.org/W3128735667","https://openalex.org/W3188159106","https://openalex.org/W4220932580","https://openalex.org/W4281640376","https://openalex.org/W4283076324","https://openalex.org/W4285103029","https://openalex.org/W4321482580","https://openalex.org/W4362714630","https://openalex.org/W4376606783","https://openalex.org/W4385525163","https://openalex.org/W4385532589","https://openalex.org/W4385541400","https://openalex.org/W4386763434","https://openalex.org/W4387187489","https://openalex.org/W4394712189","https://openalex.org/W4394859351","https://openalex.org/W4396674255","https://openalex.org/W4399120098","https://openalex.org/W4400034003","https://openalex.org/W4400034163","https://openalex.org/W4400034182","https://openalex.org/W4400034430","https://openalex.org/W4403420601","https://openalex.org/W4403420827","https://openalex.org/W4403421153","https://openalex.org/W4403924043"],"related_works":[],"abstract_inverted_index":{"Three-dimensional":[0],"integration":[1,33],"technologies":[2],"present":[3],"a":[4,28,44],"promising":[5],"path":[6],"forward":[7],"for":[8,31,47,59,148],"extending":[9],"Moore\u2019s":[10],"law,":[11],"facilitating":[12],"high-density":[13],"interconnects":[14],"between":[15],"chips":[16],"and":[17,50,80,90,128,144,152],"supporting":[18],"multi-tier":[19],"architectural":[20],"designs.":[21],"Cu-Cu":[22],"hybrid":[23,53,146],"bonding":[24,54,140,147],"has":[25],"emerged":[26],"as":[27,161],"favored":[29],"technique":[30],"the":[32,92,95,100,120,137,154],"of":[34,94,122,139,156],"chiplets":[35],"at":[36],"high":[37],"interconnect":[38],"density.":[39,82,165],"This":[40],"paper":[41],"introduces":[42],"YAP,":[43],"yield":[45,66,88,97],"model":[46,57,98],"wafer-to-wafer":[48],"(W2W)":[49],"die-to-wafer":[51],"(D2W)":[52],"process.":[55],"The":[56,103],"accounts":[58],"key":[60],"failure":[61],"mechanisms":[62],"that":[63,106],"contribute":[64],"to":[65,135],"loss,":[67],"including":[68],"overlay":[69],"errors,":[70],"particle":[71,163],"defects,":[72],"Cu":[73,81],"recess":[74],"variations,":[75],"excessive":[76],"wafer":[77],"surface":[78],"roughness,":[79],"We":[83,132],"also":[84],"develop":[85],"an":[86],"open-source":[87],"simulator":[89],"compare":[91,142],"accuracy":[93,111],"near-analytical":[96],"with":[99],"simulation":[101],"results.":[102],"results":[104],"demonstrate":[105],"YAP":[107,118,134],"achieves":[108],"virtually":[109],"identical":[110],"while":[112],"offering":[113],"over":[114],"10,000x":[115],"faster":[116],"runtime.":[117],"enables":[119],"co-optimization":[121],"packaging":[123],"technologies,":[124],"assembly":[125],"design":[126,130],"rules,":[127],"overall":[129],"methodologies.":[131],"used":[133],"examine":[136],"impact":[138],"pitch,":[141],"W2W":[143],"D2W":[145],"varying":[149],"chiplet":[150],"sizes,":[151],"explore":[153],"benefits":[155],"tighter":[157],"process":[158],"controls,":[159],"such":[160],"improved":[162],"defect":[164]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}
