{"id":"https://openalex.org/W4386764089","doi":"https://doi.org/10.1109/dac56929.2023.10247841","title":"PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table","display_name":"PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table","publication_year":2023,"publication_date":"2023-07-09","ids":{"openalex":"https://openalex.org/W4386764089","doi":"https://doi.org/10.1109/dac56929.2023.10247841"},"language":"en","primary_location":{"id":"doi:10.1109/dac56929.2023.10247841","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/dac56929.2023.10247841","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 60th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104169607","display_name":"JaeHwa Jeon","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"JaeHwa Jeon","raw_affiliation_strings":["Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113001549","display_name":"Jae-Youn Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jae-Youn Hong","raw_affiliation_strings":["Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100429324","display_name":"Sung\u2010Hoon Kim","orcid":"https://orcid.org/0000-0002-1570-3230"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sunghoon Kim","raw_affiliation_strings":["Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089569520","display_name":"In\u2010Su Choi","orcid":"https://orcid.org/0000-0001-7002-6853"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Insu Choi","raw_affiliation_strings":["Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026627679","display_name":"Joon-Sung Yang","orcid":"https://orcid.org/0000-0002-1502-5353"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Joon-Sung Yang","raw_affiliation_strings":["Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","Department of Systems Semiconductor Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yonsei University,Department of Electrical and Electronic Engineering,Seoul,South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Systems Semiconductor Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12649098,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"39","issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8531912565231323},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8303185701370239},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.8264408707618713},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.6341071128845215},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6067075729370117},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5814358592033386},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.569190263748169},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5580913424491882},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.526125431060791},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4885445535182953},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4459995925426483},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.44012850522994995},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.43192532658576965},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4281827211380005},{"id":"https://openalex.org/keywords/performance-improvement","display_name":"Performance improvement","score":0.4271390736103058},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.42678698897361755},{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.418783962726593},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3930944502353668},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3582024574279785},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.271317720413208},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.25811558961868286},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08279964327812195},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.06361925601959229}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8531912565231323},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8303185701370239},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.8264408707618713},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.6341071128845215},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6067075729370117},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5814358592033386},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.569190263748169},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5580913424491882},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.526125431060791},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4885445535182953},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4459995925426483},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.44012850522994995},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.43192532658576965},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4281827211380005},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.4271390736103058},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.42678698897361755},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.418783962726593},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3930944502353668},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3582024574279785},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.271317720413208},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.25811558961868286},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08279964327812195},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.06361925601959229},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac56929.2023.10247841","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/dac56929.2023.10247841","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 60th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2147657366","https://openalex.org/W2809491099","https://openalex.org/W2943020811","https://openalex.org/W3092614054"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2065759842","https://openalex.org/W2185658074","https://openalex.org/W2557931434","https://openalex.org/W2555826082","https://openalex.org/W2907559171","https://openalex.org/W2809388636","https://openalex.org/W4233769243","https://openalex.org/W2155643858","https://openalex.org/W2129513794"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3],"novel":[4],"memory":[5,34,42,45,63,70],"architecture,":[6],"PIE-DRAM,":[7],"to":[8,28,53],"mitigate":[9],"the":[10,20,49,58,62,84,89],"performance":[11],"overhead":[12],"caused":[13],"by":[14,82],"IECC.":[15],"Unlike":[16],"conventional":[17],"IECC":[18,24,31,52,55],"architectures,":[19],"proposed":[21,59,85],"method":[22],"separates":[23],"from":[25,33,69],"data":[26],"path":[27],"enable":[29],"independent":[30],"operations":[32],"read":[35],"or":[36],"write":[37],"access.":[38],"Based":[39],"on":[40],"recent":[41],"access":[43],"histories,":[44],"controller":[46],"selectively":[47],"determines":[48],"usage":[50],"of":[51],"alleviate":[54],"overhead,":[56],"thereby":[57],"architecture":[60,87],"enhances":[61],"performance.":[64],"Experimental":[65],"results":[66],"show":[67],"that,":[68],"intensive":[71],"workloads,":[72],"6%":[73],"IPC":[74],"(Instructions":[75],"Per":[76],"Cycle)":[77],"improvement":[78],"is":[79],"achieved":[80],"solely":[81],"applying":[83],"DRAM":[86],"utilizing":[88],"locality":[90],"and":[91],"modified":[92],"RMW.":[93]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
