{"id":"https://openalex.org/W3213391152","doi":"https://doi.org/10.1109/dac18074.2021.9586243","title":"Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems","display_name":"Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems","publication_year":2021,"publication_date":"2021-11-08","ids":{"openalex":"https://openalex.org/W3213391152","doi":"https://doi.org/10.1109/dac18074.2021.9586243","mag":"3213391152"},"language":"en","primary_location":{"id":"doi:10.1109/dac18074.2021.9586243","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18074.2021.9586243","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 58th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006491300","display_name":"Srinivas Bodapati","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Srinivas Bodapati","raw_affiliation_strings":["Intel Corp"],"affiliations":[{"raw_affiliation_string":"Intel Corp","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077642267","display_name":"P. Ranade","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Pushkar Ranade","raw_affiliation_strings":["Intel Corp"],"affiliations":[{"raw_affiliation_string":"Intel Corp","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040314189","display_name":"Ramune Nagisetty","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Ramune Nagisetty","raw_affiliation_strings":["Intel Corp"],"affiliations":[{"raw_affiliation_string":"Intel Corp","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5006491300"],"corresponding_institution_ids":["https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":0.1003,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.4483187,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"9","issue":null,"first_page":"1307","last_page":"1310"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.7688949108123779},{"id":"https://openalex.org/keywords/semiconductor-device-fabrication","display_name":"Semiconductor device fabrication","score":0.6155086159706116},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5455933213233948},{"id":"https://openalex.org/keywords/manufacturing-engineering","display_name":"Manufacturing engineering","score":0.5331805348396301},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4837493896484375},{"id":"https://openalex.org/keywords/systems-architecture","display_name":"Systems architecture","score":0.4760596454143524},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.4437108337879181},{"id":"https://openalex.org/keywords/computer-integrated-manufacturing","display_name":"Computer-integrated manufacturing","score":0.4427809715270996},{"id":"https://openalex.org/keywords/manufacturing-process","display_name":"Manufacturing process","score":0.44101932644844055},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.43234729766845703},{"id":"https://openalex.org/keywords/process-development-execution-system","display_name":"Process development execution system","score":0.43097907304763794},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42460885643959045},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37241092324256897},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.3637199401855469},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.34330302476882935},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09300807118415833},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08272737264633179}],"concepts":[{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.7688949108123779},{"id":"https://openalex.org/C66018809","wikidata":"https://www.wikidata.org/wiki/Q1570432","display_name":"Semiconductor device fabrication","level":3,"score":0.6155086159706116},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5455933213233948},{"id":"https://openalex.org/C117671659","wikidata":"https://www.wikidata.org/wiki/Q11049265","display_name":"Manufacturing engineering","level":1,"score":0.5331805348396301},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4837493896484375},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.4760596454143524},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.4437108337879181},{"id":"https://openalex.org/C53688548","wikidata":"https://www.wikidata.org/wiki/Q1122190","display_name":"Computer-integrated manufacturing","level":2,"score":0.4427809715270996},{"id":"https://openalex.org/C2987875673","wikidata":"https://www.wikidata.org/wiki/Q187939","display_name":"Manufacturing process","level":2,"score":0.44101932644844055},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.43234729766845703},{"id":"https://openalex.org/C201547687","wikidata":"https://www.wikidata.org/wiki/Q7247240","display_name":"Process development execution system","level":3,"score":0.43097907304763794},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42460885643959045},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37241092324256897},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.3637199401855469},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34330302476882935},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09300807118415833},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08272737264633179},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac18074.2021.9586243","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18074.2021.9586243","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 58th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6000000238418579,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2035907685","https://openalex.org/W2085621559","https://openalex.org/W2115540908","https://openalex.org/W2116341502","https://openalex.org/W2145929661","https://openalex.org/W2503057153","https://openalex.org/W2790721814","https://openalex.org/W3006667757","https://openalex.org/W3013062889","https://openalex.org/W3016874508","https://openalex.org/W3080132014","https://openalex.org/W3113090643","https://openalex.org/W4254713093","https://openalex.org/W4256167503","https://openalex.org/W6677553139","https://openalex.org/W6787026827"],"related_works":["https://openalex.org/W2154320603","https://openalex.org/W2534971964","https://openalex.org/W2006997784","https://openalex.org/W2152072926","https://openalex.org/W2377019842","https://openalex.org/W2538238774","https://openalex.org/W1985037053","https://openalex.org/W2376711239","https://openalex.org/W2349171008","https://openalex.org/W2055811822"],"abstract_inverted_index":{"AI/ML":[0,55,72],"systems":[1,19,56],"have":[2,20],"been":[3,21],"deployed":[4],"in":[5,12,40],"both":[6],"SoC":[7,59],"design/architecture":[8],"as":[9,11],"well":[10],"semiconductor":[13],"manufacturing":[14,62,76],"over":[15],"the":[16,32,44],"years.":[17],"These":[18],"independent":[22],"of":[23,46,69],"each":[24],"other":[25],"with":[26],"process":[27],"design":[28,35,78],"kits":[29],"(PDK)":[30],"being":[31],"interface":[33],"between":[34],"and":[36,43,61,77],"manufacturing.":[37],"Recent":[38],"advances":[39],"packaging":[41],"technology":[42],"adoption":[45],"chiplet":[47,82],"architecture":[48,60,83],"has":[49],"opened":[50],"exciting":[51],"avenues":[52],"for":[53,81],"merged":[54],"that":[57,74],"bring":[58],"together.":[63],"This":[64],"work":[65],"explores":[66],"this":[67],"opportunity":[68],"enabling":[70],"an":[71],"system":[73],"brings":[75],"information":[79],"together":[80],"exploration":[84]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}