{"id":"https://openalex.org/W3214138519","doi":"https://doi.org/10.1109/dac18074.2021.9586132","title":"LUT-Based Optimization For ASIC Design Flow","display_name":"LUT-Based Optimization For ASIC Design Flow","publication_year":2021,"publication_date":"2021-11-08","ids":{"openalex":"https://openalex.org/W3214138519","doi":"https://doi.org/10.1109/dac18074.2021.9586132","mag":"3214138519"},"language":"en","primary_location":{"id":"doi:10.1109/dac18074.2021.9586132","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18074.2021.9586132","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 58th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/290676","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023405941","display_name":"Luca Amar\u00f9","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Luca Amaru","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031641596","display_name":"Vinicius N. Possani","orcid":"https://orcid.org/0000-0003-4334-1174"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vinicius Possani","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033842260","display_name":"Eleonora Testa","orcid":"https://orcid.org/0000-0003-1114-8476"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eleonora Testa","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010444815","display_name":"Felipe S. Marranghello","orcid":"https://orcid.org/0000-0002-5368-6750"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Felipe Marranghello","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062594016","display_name":"Christopher Casares","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher Casares","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015217224","display_name":"Jiong Luo","orcid":"https://orcid.org/0009-0006-2158-5804"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiong Luo","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006756374","display_name":"Patrick Vuillod","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patrick Vuillod","raw_affiliation_strings":["Synopsys Inc., Design Group, Sunnyvale, California, USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc., Design Group, Sunnyvale, California, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["University of California, Berkeley, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Integrated Systems Laboratory, EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5023405941"],"corresponding_institution_ids":["https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":1.612,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.83543705,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"871","last_page":"876"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8942128419876099},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.749878466129303},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.687818169593811},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6698867678642273},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5273129343986511},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5036687254905701},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4702025055885315},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.45810532569885254},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45150646567344666},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.33146119117736816},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29062509536743164},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2778628468513489}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8942128419876099},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.749878466129303},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.687818169593811},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6698867678642273},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5273129343986511},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5036687254905701},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4702025055885315},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.45810532569885254},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45150646567344666},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.33146119117736816},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29062509536743164},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2778628468513489},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dac18074.2021.9586132","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18074.2021.9586132","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 58th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:290676","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/290676","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference proceedings"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:290676","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/290676","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference proceedings"},"sustainable_development_goals":[{"score":0.6000000238418579,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W123380697","https://openalex.org/W1511688816","https://openalex.org/W1528837436","https://openalex.org/W1612810659","https://openalex.org/W1993932586","https://openalex.org/W2018094844","https://openalex.org/W2025617772","https://openalex.org/W2035561773","https://openalex.org/W2097830678","https://openalex.org/W2100955320","https://openalex.org/W2105715355","https://openalex.org/W2105761964","https://openalex.org/W2106950603","https://openalex.org/W2127856935","https://openalex.org/W2129183345","https://openalex.org/W2133431298","https://openalex.org/W2133559461","https://openalex.org/W2138265054","https://openalex.org/W2159081664","https://openalex.org/W2167328871","https://openalex.org/W2242458479","https://openalex.org/W2786101043","https://openalex.org/W2898100868","https://openalex.org/W2908839997","https://openalex.org/W2945283099","https://openalex.org/W4239323126","https://openalex.org/W6636505876","https://openalex.org/W6755426828"],"related_works":["https://openalex.org/W2070693700","https://openalex.org/W2097839191","https://openalex.org/W2132107645","https://openalex.org/W3200538824","https://openalex.org/W2505126014","https://openalex.org/W2014496217","https://openalex.org/W3007361144","https://openalex.org/W4231098049","https://openalex.org/W2362210492","https://openalex.org/W2144630005"],"abstract_inverted_index":{"Look-up":[0],"Table":[1],"(LUT)":[2],"mapping":[3,32,65],"and":[4,31,81,157],"optimization":[5,30,46,112,147],"is":[6,49],"an":[7],"important":[8],"step":[9],"in":[10,24,116,132,138],"Field":[11],"Programmable":[12],"Gate":[13],"Arrays":[14],"(FPGAs)":[15],"design.":[16],"The":[17],"effectiveness":[18],"of":[19,54,71,127],"LUT":[20,64,72,93,146],"synthesis":[21,53,119,135],"improved":[22],"dramatically":[23],"the":[25,52,68,85,128,133],"last":[26],"decades,":[27],"thanks":[28],"to":[29,66,79],"innovations":[33],"naturally":[34],"tailored":[35,50],"for":[36,51,143],"FPGAs.":[37,61],"In":[38],"this":[39],"paper,":[40],"we":[41,124],"develop":[42],"a":[43,97,117,139],"new":[44],"LUT-based":[45,111],"flow":[47,142],"that":[48],"Application-Specific":[55],"Integrated":[56],"Circuits":[57],"(ASICs)":[58],"rather":[59],"than":[60],"We":[62,74,107],"enhance":[63],"consider":[67],"literal/AIG":[69],"cost":[70],"nodes.":[73],"extend":[75],"traditional":[76],"Boolean":[77,104],"methods":[78],"simplify":[80],"re-shape":[82],"LUT-networks,":[83],"targeting":[84],"best":[86,129],"AIG/mapped-network":[87],"implementation,":[88,164],"after":[89,162],"decomposition.":[90],"Intuitively,":[91],"literal-driven":[92],"packing":[94],"behaves":[95],"as":[96],"powerful":[98],"fanin-bound":[99],"node":[100],"elimination,":[101],"unveiling":[102],"higher-order":[103],"simplification":[105],"opportunities.":[106],"embed":[108],"our":[109,122,145],"proposed":[110],"flow,":[113],"area":[114,130,149],"oriented,":[115],"commercial":[118,140],"tool.":[120],"Using":[121],"methodology,":[123],"improve":[125],"12":[126],"results":[131],"EPFL":[134],"competition.":[136],"Employed":[137],"EDA":[141],"ASICs,":[144],"reduces":[148],"by":[150,155,160],"1.80%,":[151],"total":[152],"negative":[153],"slack":[154],"0.39%,":[156],"switching":[158],"power":[159],"1.72%,":[161],"physical":[163],"at":[165],"5%":[166],"runtime":[167],"cost.":[168]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
