{"id":"https://openalex.org/W3212441214","doi":"https://doi.org/10.1109/dac18074.2021.9586130","title":"UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling","display_name":"UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling","publication_year":2021,"publication_date":"2021-11-08","ids":{"openalex":"https://openalex.org/W3212441214","doi":"https://doi.org/10.1109/dac18074.2021.9586130","mag":"3212441214"},"language":"en","primary_location":{"id":"doi:10.1109/dac18074.2021.9586130","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18074.2021.9586130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 58th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020519671","display_name":"Shunning Jiang","orcid":"https://orcid.org/0000-0003-3439-5760"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shunning Jiang","raw_affiliation_strings":["School of Electrical and Computer Engineering, Cornell University, Ithaca, NY"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Cornell University, Ithaca, NY","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033494020","display_name":"Yanghui Ou","orcid":"https://orcid.org/0000-0001-9481-9882"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yanghui Ou","raw_affiliation_strings":["School of Electrical and Computer Engineering, Cornell University, Ithaca, NY"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Cornell University, Ithaca, NY","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082177621","display_name":"Peitian Pan","orcid":"https://orcid.org/0000-0001-6147-9092"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peitian Pan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Cornell University, Ithaca, NY"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Cornell University, Ithaca, NY","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091660287","display_name":"Christopher Batten","orcid":"https://orcid.org/0000-0002-2835-667X"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher Batten","raw_affiliation_strings":["School of Electrical and Computer Engineering, Cornell University, Ithaca, NY"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Cornell University, Ithaca, NY","institution_ids":["https://openalex.org/I205783295"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5020519671"],"corresponding_institution_ids":["https://openalex.org/I205783295"],"apc_list":null,"apc_paid":null,"fwci":0.4606,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61060271,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"883","last_page":"888"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.7818151712417603},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7578260898590088},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6103876829147339},{"id":"https://openalex.org/keywords/python","display_name":"Python (programming language)","score":0.5774781703948975},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5521376729011536},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5158135294914246},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49005305767059326},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.44487422704696655},{"id":"https://openalex.org/keywords/fidelity","display_name":"Fidelity","score":0.44175273180007935},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.43652021884918213},{"id":"https://openalex.org/keywords/formalism","display_name":"Formalism (music)","score":0.4149734079837799},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3934444189071655},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3851885497570038},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.357855886220932},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2889682948589325},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.26227349042892456},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2309677004814148},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.22879698872566223},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.15043434500694275},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.11604121327400208},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10207945108413696}],"concepts":[{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.7818151712417603},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7578260898590088},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6103876829147339},{"id":"https://openalex.org/C519991488","wikidata":"https://www.wikidata.org/wiki/Q28865","display_name":"Python (programming language)","level":2,"score":0.5774781703948975},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5521376729011536},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5158135294914246},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49005305767059326},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.44487422704696655},{"id":"https://openalex.org/C2776459999","wikidata":"https://www.wikidata.org/wiki/Q2119376","display_name":"Fidelity","level":2,"score":0.44175273180007935},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.43652021884918213},{"id":"https://openalex.org/C73301696","wikidata":"https://www.wikidata.org/wiki/Q5469984","display_name":"Formalism (music)","level":3,"score":0.4149734079837799},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3934444189071655},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3851885497570038},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.357855886220932},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2889682948589325},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.26227349042892456},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2309677004814148},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.22879698872566223},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.15043434500694275},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.11604121327400208},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10207945108413696},{"id":"https://openalex.org/C558565934","wikidata":"https://www.wikidata.org/wiki/Q2743","display_name":"Musical","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac18074.2021.9586130","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18074.2021.9586130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 58th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1976890955","https://openalex.org/W1979527452","https://openalex.org/W2010074783","https://openalex.org/W2079751107","https://openalex.org/W2113167168","https://openalex.org/W2118231264","https://openalex.org/W2140321074","https://openalex.org/W2147657366","https://openalex.org/W2157225945","https://openalex.org/W2162639668","https://openalex.org/W2170382128","https://openalex.org/W2185943396","https://openalex.org/W2762155252","https://openalex.org/W2809084326","https://openalex.org/W3031264475","https://openalex.org/W4242312330","https://openalex.org/W4244062578","https://openalex.org/W6825444808"],"related_works":["https://openalex.org/W4241206086","https://openalex.org/W2543290882","https://openalex.org/W2109697164","https://openalex.org/W1528726807","https://openalex.org/W1964556228","https://openalex.org/W809008615","https://openalex.org/W3047975009","https://openalex.org/W2156420848","https://openalex.org/W1905101075","https://openalex.org/W3021846743"],"abstract_inverted_index":{"We":[0,93],"propose":[1],"unified":[2],"modular":[3],"ordering":[4,69,80,88],"constraints":[5,81,89],"(UMOC),":[6],"a":[7,100],"novel":[8],"approach":[9],"that":[10],"seamlessly":[11],"unifies":[12],"method-based":[13],"cycle-level":[14],"(CL)":[15],"modeling":[16,29,49,105],"and":[17,31,44,50,56,85,95],"signal-based":[18],"register-transfer-level":[19],"(RTL)":[20],"modeling.":[21],"Motivated":[22],"by":[23],"the":[24,39,62,66],"challenges":[25],"in":[26,98],"state-of-the-art":[27,101],"CL":[28,48,55,91],"methodologies":[30],"existing":[32],"CL/RTL":[33],"composition":[34,53],"attempts,":[35],"UMOC":[36,73,97],"successfully":[37],"breaks":[38],"trade-off":[40],"between":[41],"model":[42],"fidelity":[43],"scheduling":[45],"modularity":[46],"for":[47],"provides":[51],"seamless":[52],"of":[54,60,70,82,90],"RTL":[57,83],"models.":[58],"Instead":[59],"requiring":[61],"designer":[63],"to":[64],"specify":[65],"global":[67],"intra-cycle":[68],"hardware":[71,104],"processes,":[72],"eliminates":[74],"this":[75],"burden":[76],"using":[77],"implicit":[78],"local":[79,87],"signals":[84],"explicit":[86],"methods.":[92],"implement":[94],"evaluate":[96],"PyMTL3,":[99],"open-source":[102],"Python-based":[103],"framework.":[106]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
