{"id":"https://openalex.org/W3091791413","doi":"https://doi.org/10.1109/dac18072.2020.9218612","title":"WET: Write Efficient Loop Tiling for Non-Volatile Main Memory","display_name":"WET: Write Efficient Loop Tiling for Non-Volatile Main Memory","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3091791413","doi":"https://doi.org/10.1109/dac18072.2020.9218612","mag":"3091791413"},"language":"en","primary_location":{"id":"doi:10.1109/dac18072.2020.9218612","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18072.2020.9218612","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038435788","display_name":"Mohammad Alshboul","orcid":"https://orcid.org/0009-0008-3603-1729"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mohammad Alshboul","raw_affiliation_strings":["North Carolina State University, Raleigh, NC"],"affiliations":[{"raw_affiliation_string":"North Carolina State University, Raleigh, NC","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066115006","display_name":"James Tuck","orcid":"https://orcid.org/0000-0001-8975-0294"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James Tuck","raw_affiliation_strings":["North Carolina State University, Raleigh, NC"],"affiliations":[{"raw_affiliation_string":"North Carolina State University, Raleigh, NC","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061775189","display_name":"Yan Solihin","orcid":"https://orcid.org/0000-0002-8863-941X"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yan Solihin","raw_affiliation_strings":["University of Central Florida, Orlando, FL"],"affiliations":[{"raw_affiliation_string":"University of Central Florida, Orlando, FL","institution_ids":["https://openalex.org/I106165777"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5038435788"],"corresponding_institution_ids":["https://openalex.org/I137902535"],"apc_list":null,"apc_paid":null,"fwci":0.6931,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68118467,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8409608602523804},{"id":"https://openalex.org/keywords/loop-tiling","display_name":"Loop tiling","score":0.7082431316375732},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6892693042755127},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6376916170120239},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5492900013923645},{"id":"https://openalex.org/keywords/loop-optimization","display_name":"Loop optimization","score":0.5472055673599243},{"id":"https://openalex.org/keywords/matrix-multiplication","display_name":"Matrix multiplication","score":0.5292408466339111},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.39911410212516785},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18006905913352966}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8409608602523804},{"id":"https://openalex.org/C11799548","wikidata":"https://www.wikidata.org/wiki/Q6675847","display_name":"Loop tiling","level":3,"score":0.7082431316375732},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6892693042755127},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6376916170120239},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5492900013923645},{"id":"https://openalex.org/C29331672","wikidata":"https://www.wikidata.org/wiki/Q3354468","display_name":"Loop optimization","level":4,"score":0.5472055673599243},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.5292408466339111},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.39911410212516785},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18006905913352966},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac18072.2020.9218612","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18072.2020.9218612","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W143350511","https://openalex.org/W1926816778","https://openalex.org/W1971065013","https://openalex.org/W1983826793","https://openalex.org/W2041135949","https://openalex.org/W2042629708","https://openalex.org/W2065457989","https://openalex.org/W2073061372","https://openalex.org/W2093783472","https://openalex.org/W2095875205","https://openalex.org/W2096800126","https://openalex.org/W2098463429","https://openalex.org/W2102449048","https://openalex.org/W2117169958","https://openalex.org/W2119609467","https://openalex.org/W2124480634","https://openalex.org/W2126464777","https://openalex.org/W2127927771","https://openalex.org/W2149668662","https://openalex.org/W2171888576","https://openalex.org/W2521305513","https://openalex.org/W2570467259","https://openalex.org/W2610308442","https://openalex.org/W2755734538","https://openalex.org/W2765864547","https://openalex.org/W2766455145","https://openalex.org/W2769005600","https://openalex.org/W2947555139","https://openalex.org/W2964106805","https://openalex.org/W3105209461"],"related_works":["https://openalex.org/W2014071052","https://openalex.org/W1549990549","https://openalex.org/W3169195854","https://openalex.org/W2244841219","https://openalex.org/W2010414531","https://openalex.org/W1498734356","https://openalex.org/W4256622436","https://openalex.org/W4247745956","https://openalex.org/W2100888070","https://openalex.org/W2374990197"],"abstract_inverted_index":{"Future":[0],"systems":[1],"are":[2],"expected":[3],"to":[4,14,35,38,93,126,132,138],"increasingly":[5],"include":[6],"a":[7,68,85,115],"Non-Volatile":[8],"Main":[9],"Memory":[10],"(NVMM).":[11],"However,":[12],"due":[13],"the":[15,20,47,58,101,122,127,134],"limited":[16],"NVMM":[17,97],"write":[18,87,123],"endurance,":[19],"number":[21,135],"of":[22,49,60,136],"writes":[23,37,137,143],"must":[24],"be":[25],"reduced.":[26],"While":[27],"new":[28,116],"architectures":[29],"and":[30,105],"algorithms":[31],"have":[32,44],"been":[33],"proposed":[34],"reduce":[36,133,142],"NVMM,":[39],"few":[40],"or":[41],"no":[42],"studies":[43],"looked":[45],"at":[46],"effect":[48],"compiler":[50,63],"optimizations":[51],"on":[52,67,81],"writes.In":[53],"this":[54],"paper,":[55],"we":[56,90],"investigate":[57,91],"impact":[59],"one":[61],"popular":[62],"optimization":[64],"(loop":[65],"tiling)":[66],"very":[69],"important":[70],"computation":[71],"kernel":[72],"(matrix":[73],"multiplication).":[74],"Our":[75,109,140],"novel":[76],"observation":[77],"includes":[78],"that":[79],"tiling":[80],"matrix":[82],"multiplication":[83],"causes":[84],"25\u00d7":[86],"amplification.":[88],"Furthermore,":[89],"techniques":[92],"make":[94],"tilling":[95],"more":[96],"friendly,":[98],"through":[99],"choosing":[100],"right":[102],"tile":[103,118],"size":[104],"employing":[106],"hierarchical":[107],"tiling.":[108],"method":[110],"Write-Efficient":[111],"Tiling":[112],"(WET)":[113],"adds":[114],"outer":[117],"designed":[119],"for":[120],"fitting":[121],"working":[124],"set":[125],"Last":[128],"Level":[129],"Cache":[130],"(LLC)":[131],"NVMM.":[139],"experiments":[141],"by":[144],"81%":[145],"while":[146],"simultaneously":[147],"improve":[148],"performance.":[149]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
