{"id":"https://openalex.org/W3092302326","doi":"https://doi.org/10.1109/dac18072.2020.9218569","title":"Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification","display_name":"Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3092302326","doi":"https://doi.org/10.1109/dac18072.2020.9218569","mag":"3092302326"},"language":"en","primary_location":{"id":"doi:10.1109/dac18072.2020.9218569","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18072.2020.9218569","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002478857","display_name":"Peng Zou","orcid":"https://orcid.org/0000-0002-8345-0976"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Peng Zou","raw_affiliation_strings":["College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","State Key Lab of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]},{"raw_affiliation_string":"State Key Lab of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101664594","display_name":"Zhifeng Lin","orcid":"https://orcid.org/0000-0002-4597-4322"},"institutions":[{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhifeng Lin","raw_affiliation_strings":["College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China"],"affiliations":[{"raw_affiliation_string":"College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Xiao Shi","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiao Shi","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102004960","display_name":"Yingjie Wu","orcid":"https://orcid.org/0000-0002-5201-3159"},"institutions":[{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yingjie Wu","raw_affiliation_strings":["College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China"],"affiliations":[{"raw_affiliation_string":"College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101854580","display_name":"Jianli Chen","orcid":"https://orcid.org/0000-0002-1391-2696"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianli Chen","raw_affiliation_strings":["College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","State Key Lab of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]},{"raw_affiliation_string":"State Key Lab of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103098516","display_name":"Jun Yu","orcid":"https://orcid.org/0000-0003-4286-9292"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Yu","raw_affiliation_strings":["State Key Lab of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5002478857"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I80947539"],"apc_list":null,"apc_paid":null,"fwci":1.6501,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.84209784,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7514607906341553},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7330195903778076},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7095840573310852},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.5127719044685364},{"id":"https://openalex.org/keywords/time-division-multiplexing","display_name":"Time-division multiplexing","score":0.4364651143550873},{"id":"https://openalex.org/keywords/weighting","display_name":"Weighting","score":0.42925578355789185},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38069307804107666},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3534920811653137},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.33470839262008667},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0868566632270813}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7514607906341553},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7330195903778076},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7095840573310852},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.5127719044685364},{"id":"https://openalex.org/C50661577","wikidata":"https://www.wikidata.org/wiki/Q901831","display_name":"Time-division multiplexing","level":3,"score":0.4364651143550873},{"id":"https://openalex.org/C183115368","wikidata":"https://www.wikidata.org/wiki/Q856577","display_name":"Weighting","level":2,"score":0.42925578355789185},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38069307804107666},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3534920811653137},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.33470839262008667},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0868566632270813},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C126838900","wikidata":"https://www.wikidata.org/wiki/Q77604","display_name":"Radiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac18072.2020.9218569","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18072.2020.9218569","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1975290397","https://openalex.org/W1990317614","https://openalex.org/W1992578807","https://openalex.org/W2017927472","https://openalex.org/W2030959856","https://openalex.org/W2032699516","https://openalex.org/W2054922540","https://openalex.org/W2056692632","https://openalex.org/W2075490772","https://openalex.org/W2121066557","https://openalex.org/W2171071906","https://openalex.org/W2227557434","https://openalex.org/W2261042505","https://openalex.org/W2401610261","https://openalex.org/W2772001064","https://openalex.org/W2789489838","https://openalex.org/W2899799513","https://openalex.org/W2964929543"],"related_works":["https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W431360389","https://openalex.org/W4318684556","https://openalex.org/W1998182654","https://openalex.org/W2258948885","https://openalex.org/W2184011203","https://openalex.org/W181065026","https://openalex.org/W2187051616","https://openalex.org/W2111804337"],"abstract_inverted_index":{"Multi-FPGA":[0],"prototyping":[1],"is":[2,32,131,145,173],"widely":[3],"used":[4],"for":[5],"modern":[6],"VLSI":[7],"verification,":[8],"but":[9],"the":[10,27,44,50,58,67,84,93,99,105,123,132,150,178,183,187,195,206],"limited":[11],"number":[12,133],"of":[13,60,134],"inter-FPGA":[14,68],"connections":[15],"in":[16,136],"a":[17,25,62,76,109,141,158,169],"multi-FPGA":[18],"system":[19,63],"may":[20],"cause":[21],"routing":[22,46,69,79,100,107,154],"failures.":[23],"As":[24],"result,":[26],"time-division":[28],"multiplexing":[29],"(TDM)":[30],"technique":[31,172],"adopted":[33],"to":[34,49,81,147,153,162,175],"increase":[35],"its":[36],"resource":[37],"utilization":[38],"by":[39,157],"transmitting":[40],"multiple":[41],"signals":[42],"through":[43],"same":[45],"channel.":[47],"Due":[48],"large":[51],"signal":[52],"delay":[53],"between":[54],"FPGA":[55],"pairs,":[56],"however,":[57],"performance":[59,124],"such":[61],"greatly":[64],"depends":[65],"on":[66,194],"quality.":[70,180],"In":[71],"this":[72],"paper,":[73],"we":[74,102],"propose":[75],"TDM-based":[77],"system-level":[78],"algorithm":[80,121,161,204],"simultaneously":[82],"minimize":[83],"maximum":[85],"TDM":[86,151,210,215],"(signal":[87],"multiplexing)":[88],"ratio":[89,95,152,211],"and":[90,115,209],"runtime,":[91],"considering":[92],"crucial":[94],"constraints.":[96,216],"By":[97],"weighting":[98],"edges,":[101],"first":[103],"model":[104],"net":[106,166],"as":[108],"Steiner":[110],"minimum":[111],"tree":[112],"(SMT)":[113],"problem":[114],"solve":[116],"it":[117],"with":[118,122,182],"an":[119,137],"approximation":[120],"bound":[125],"2(1":[126],"-":[127],"1/1),":[128],"where":[129],"l":[130],"leaves":[135],"optimal":[138],"SMT.":[139],"Then,":[140],"timing-driven":[142],"assignment":[143],"method":[144],"presented":[146],"evenly":[148],"distribute":[149],"signals,":[155],"followed":[156],"novel":[159],"reassignment":[160],"efficiently":[163],"handle":[164],"unbalanced":[165],"groups.":[167],"Finally,":[168],"ratio-aware":[170],"refinement":[171],"employed":[174],"further":[176],"improve":[177],"solution":[179],"Compared":[181],"top-3":[184],"winners":[185],"at":[186,191],"2019":[188],"CAD":[189],"Contest":[190],"ICCAD":[192],"based":[193],"contest":[196],"benchmarks,":[197],"experiment":[198],"results":[199],"show":[200],"that":[201],"our":[202],"proposed":[203],"achieves":[205],"best":[207],"runtime":[208],"while":[212],"satisfying":[213],"all":[214]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}
