{"id":"https://openalex.org/W3091856741","doi":"https://doi.org/10.1109/dac18072.2020.9218552","title":"Time Multiplexing via Circuit Folding","display_name":"Time Multiplexing via Circuit Folding","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3091856741","doi":"https://doi.org/10.1109/dac18072.2020.9218552","mag":"3091856741"},"language":"en","primary_location":{"id":"doi:10.1109/dac18072.2020.9218552","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18072.2020.9218552","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039939942","display_name":"Po-Chun Chien","orcid":"https://orcid.org/0000-0001-5139-5178"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Po-Chun Chien","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, Taipei, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078604015","display_name":"Jie-Hong R. Jiang","orcid":"https://orcid.org/0000-0002-2279-4732"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jie-Hong R. Jiang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, Taipei, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5039939942"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14184088,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.8260552883148193},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.750786542892456},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7105975151062012},{"id":"https://openalex.org/keywords/time-division-multiplexing","display_name":"Time-division multiplexing","score":0.5905041098594666},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5739596486091614},{"id":"https://openalex.org/keywords/folding","display_name":"Folding (DSP implementation)","score":0.4873958230018616},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.44017454981803894},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4194129407405853},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4147724509239197},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4015111029148102},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3944323658943176},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.24286198616027832},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23104017972946167},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17307725548744202},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16715151071548462},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13241088390350342},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10148864984512329}],"concepts":[{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.8260552883148193},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.750786542892456},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7105975151062012},{"id":"https://openalex.org/C50661577","wikidata":"https://www.wikidata.org/wiki/Q901831","display_name":"Time-division multiplexing","level":3,"score":0.5905041098594666},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5739596486091614},{"id":"https://openalex.org/C2776545253","wikidata":"https://www.wikidata.org/wiki/Q5464292","display_name":"Folding (DSP implementation)","level":2,"score":0.4873958230018616},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.44017454981803894},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4194129407405853},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4147724509239197},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4015111029148102},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3944323658943176},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.24286198616027832},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23104017972946167},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17307725548744202},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16715151071548462},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13241088390350342},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10148864984512329},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac18072.2020.9218552","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac18072.2020.9218552","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1528837436","https://openalex.org/W2019084820","https://openalex.org/W2020003150","https://openalex.org/W2022898841","https://openalex.org/W2038084901","https://openalex.org/W2078740228","https://openalex.org/W2090073529","https://openalex.org/W2113005678","https://openalex.org/W2121066557","https://openalex.org/W2122867301","https://openalex.org/W2789489838","https://openalex.org/W2807181406","https://openalex.org/W2888391482","https://openalex.org/W2899799513","https://openalex.org/W2997041852"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W1977171228","https://openalex.org/W2121963733","https://openalex.org/W2170504327","https://openalex.org/W2766377030","https://openalex.org/W2041787842","https://openalex.org/W2059422871"],"abstract_inverted_index":{"Time":[0,36],"multiplexing":[1,62],"is":[2],"an":[3],"important":[4],"technique":[5],"to":[6,28,59],"overcome":[7],"the":[8,21,30,56,82,85,92],"bandwidth":[9,77],"bottleneck":[10],"of":[11,32,84,91],"limited":[12],"input-output":[13],"pins":[14],"in":[15],"FPGAs.":[16],"Most":[17],"prior":[18],"work":[19],"tackles":[20],"problem":[22],"from":[23],"a":[24,51,73],"physical":[25],"design":[26],"standpoint":[27],"minimize":[29],"number":[31],"cut":[33],"nets":[34],"or":[35,44],"Division":[37],"Multiplexing":[38],"(TDM)":[39],"ratio":[40],"through":[41,63],"circuit":[42,67],"partitioning":[43],"routing.":[45],"In":[46],"this":[47],"work,":[48],"we":[49],"formulate":[50],"new":[52,70],"orthogonal":[53],"approach":[54],"at":[55],"logic":[57],"level":[58],"achieve":[60],"time":[61],"structural":[64,86],"and":[65,78,88,97],"functional":[66,93],"folding.":[68],"The":[69],"formulation":[71],"provides":[72],"smooth":[74],"trade-off":[75],"between":[76],"throughput.":[79],"Experiments":[80],"show":[81],"effectiveness":[83],"method":[87,94],"improved":[89],"optimality":[90],"on":[95],"look-up-table":[96],"flip-flop":[98],"usage.":[99]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}