{"id":"https://openalex.org/W1605185852","doi":"https://doi.org/10.1109/csndsp16145.2010.5580463","title":"Fast and flexible pipelined multi-processor architecture for multimedia device","display_name":"Fast and flexible pipelined multi-processor architecture for multimedia device","publication_year":2010,"publication_date":"2010-07-01","ids":{"openalex":"https://openalex.org/W1605185852","doi":"https://doi.org/10.1109/csndsp16145.2010.5580463","mag":"1605185852"},"language":"en","primary_location":{"id":"doi:10.1109/csndsp16145.2010.5580463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/csndsp16145.2010.5580463","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 7th International Symposium on Communication Systems, Networks &amp; Digital Signal Processing (CSNDSP 2010)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100317754","display_name":"Minji Kim","orcid":"https://orcid.org/0000-0002-7282-8224"},"institutions":[{"id":"https://openalex.org/I148751991","display_name":"Sogang University","ror":"https://ror.org/056tn4839","country_code":"KR","type":"education","lineage":["https://openalex.org/I148751991"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Minji Kim","raw_affiliation_strings":["Department of Electronic Engineering, Sogang University, Seoul, South Korea","Sogang University, Department of Electronic Engineering, Seoul, Korea Rep"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Sogang University, Seoul, South Korea","institution_ids":["https://openalex.org/I148751991"]},{"raw_affiliation_string":"Sogang University, Department of Electronic Engineering, Seoul, Korea Rep","institution_ids":["https://openalex.org/I148751991"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100680764","display_name":"Jinyong Lee","orcid":"https://orcid.org/0000-0001-9604-8495"},"institutions":[{"id":"https://openalex.org/I148751991","display_name":"Sogang University","ror":"https://ror.org/056tn4839","country_code":"KR","type":"education","lineage":["https://openalex.org/I148751991"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jinyong Lee","raw_affiliation_strings":["Department of Electronic Engineering, Sogang University, Seoul, South Korea","Sogang University, Department of Electronic Engineering, Seoul, Korea Rep"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Sogang University, Seoul, South Korea","institution_ids":["https://openalex.org/I148751991"]},{"raw_affiliation_string":"Sogang University, Department of Electronic Engineering, Seoul, Korea Rep","institution_ids":["https://openalex.org/I148751991"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062494610","display_name":"Younglok Kim","orcid":"https://orcid.org/0000-0003-3586-1065"},"institutions":[{"id":"https://openalex.org/I148751991","display_name":"Sogang University","ror":"https://ror.org/056tn4839","country_code":"KR","type":"education","lineage":["https://openalex.org/I148751991"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Younglok Kim","raw_affiliation_strings":["Department of Electronic Engineering, Sogang University, Seoul, South Korea","Sogang University, Department of Electronic Engineering, Seoul, Korea Rep"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Sogang University, Seoul, South Korea","institution_ids":["https://openalex.org/I148751991"]},{"raw_affiliation_string":"Sogang University, Department of Electronic Engineering, Seoul, Korea Rep","institution_ids":["https://openalex.org/I148751991"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100317754"],"corresponding_institution_ids":["https://openalex.org/I148751991"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04991809,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"35","last_page":"39"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.98580002784729,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9750999808311462,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8680216073989868},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7119513750076294},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7090716361999512},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6651516556739807},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5674977898597717},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5539216995239258},{"id":"https://openalex.org/keywords/media-processor","display_name":"Media processor","score":0.5270740389823914},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.46869492530822754},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.46564990282058716},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.46352559328079224},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4578378200531006},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.440137654542923},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3656940162181854},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3355232775211334},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3251948356628418},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21820780634880066},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.09226152300834656},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.09052357077598572}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8680216073989868},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7119513750076294},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7090716361999512},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6651516556739807},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5674977898597717},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5539216995239258},{"id":"https://openalex.org/C52027705","wikidata":"https://www.wikidata.org/wiki/Q6805986","display_name":"Media processor","level":4,"score":0.5270740389823914},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.46869492530822754},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.46564990282058716},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.46352559328079224},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4578378200531006},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.440137654542923},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3656940162181854},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3355232775211334},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3251948356628418},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21820780634880066},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.09226152300834656},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.09052357077598572},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/csndsp16145.2010.5580463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/csndsp16145.2010.5580463","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 7th International Symposium on Communication Systems, Networks &amp; Digital Signal Processing (CSNDSP 2010)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6100000143051147}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2240212289","https://openalex.org/W2137561381","https://openalex.org/W3012895752","https://openalex.org/W2188936201","https://openalex.org/W1851356153","https://openalex.org/W2156139954","https://openalex.org/W2104078694","https://openalex.org/W2577729436","https://openalex.org/W1553337027","https://openalex.org/W2556885209"],"abstract_inverted_index":{"This":[0,66],"paper":[1],"proposes":[2],"a":[3,11,28,37,63],"fast":[4],"and":[5,48,73,78,84],"efficient":[6],"multi-processor":[7],"architecture":[8,94],"for":[9,55],"devices":[10],"requiring":[12],"high":[13],"speed":[14,85,103],"performance.":[15],"The":[16],"proposed":[17,93],"method":[18],"connects":[19],"four":[20],"basic":[21],"processor":[22],"modules":[23],"(BPM)":[24],"including":[25],"CPU's":[26],"in":[27,80],"pipeline":[29],"shape":[30],"to":[31,42],"enhance":[32],"execution":[33],"speed.":[34],"Also,":[35],"using":[36,62,70],"specific":[38],"BPM":[39],"selectively":[40],"regarding":[41],"multimedia":[43],"applications":[44],"increases":[45,95,104],"the":[46,89,92,99],"efficiency,":[47],"has":[49,67],"more":[50],"flexibility":[51],"by":[52],"software":[53],"implementation":[54],"needed":[56],"functions":[57],"without":[58],"hardware":[59,64],"replacement":[60],"than":[61],"accelerator.":[65],"been":[68],"implemented":[69],"Verilog":[71],"HDL":[72],"its":[74],"performance":[75],"is":[76],"compared":[77,97],"analyzed":[79],"terms":[81],"of":[82,86,91],"complexity":[83,90],"execution.":[87],"Even":[88],"20%":[96],"with":[98],"multi-core":[100],"CPU":[101],"method,":[102],"52%.":[105]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
