{"id":"https://openalex.org/W2130116292","doi":"https://doi.org/10.1109/csd.2003.1207723","title":"BHDL: circuit design in B","display_name":"BHDL: circuit design in B","publication_year":2004,"publication_date":"2004-03-02","ids":{"openalex":"https://openalex.org/W2130116292","doi":"https://doi.org/10.1109/csd.2003.1207723","mag":"2130116292"},"language":"en","primary_location":{"id":"doi:10.1109/csd.2003.1207723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/csd.2003.1207723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034230117","display_name":"Ammar Aljer","orcid":"https://orcid.org/0000-0002-1903-9824"},"institutions":[{"id":"https://openalex.org/I174424907","display_name":"Laboratoire d'Informatique Fondamentale de Lille","ror":"https://ror.org/05rhg0h08","country_code":"FR","type":"facility","lineage":["https://openalex.org/I174424907"]},{"id":"https://openalex.org/I2279609970","display_name":"Universit\u00e9 de Lille","ror":"https://ror.org/02kzqn938","country_code":"FR","type":"education","lineage":["https://openalex.org/I2279609970"]},{"id":"https://openalex.org/I44563897","display_name":"Universit\u00e9 d'Artois","ror":"https://ror.org/053x9s498","country_code":"FR","type":"education","lineage":["https://openalex.org/I44563897"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"A. Aljer","raw_affiliation_strings":["Laboratoire d'Informatique Fondamentale de Lille, France","Universit\u00e9 de Lille (EPE Universit\u00e9 de Lille. -- 42 rue Paul Duez, 59000 Lille - France)","LGCgE - Laboratoire de G\u00e9nie Civil et G\u00e9o-Environnement (LGCgE) - ULR 4515 (Universit\u00e9 d'Artois - Technoparc FUTURA - \r\n62400 BETHUNE - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'Informatique Fondamentale de Lille, France","institution_ids":["https://openalex.org/I174424907"]},{"raw_affiliation_string":"Universit\u00e9 de Lille (EPE Universit\u00e9 de Lille. -- 42 rue Paul Duez, 59000 Lille - France)","institution_ids":["https://openalex.org/I2279609970"]},{"raw_affiliation_string":"LGCgE - Laboratoire de G\u00e9nie Civil et G\u00e9o-Environnement (LGCgE) - ULR 4515 (Universit\u00e9 d'Artois - Technoparc FUTURA - \r\n62400 BETHUNE - France)","institution_ids":["https://openalex.org/I44563897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034224702","display_name":"Philippe Devienne","orcid":"https://orcid.org/0000-0002-7023-1088"},"institutions":[{"id":"https://openalex.org/I174424907","display_name":"Laboratoire d'Informatique Fondamentale de Lille","ror":"https://ror.org/05rhg0h08","country_code":"FR","type":"facility","lineage":["https://openalex.org/I174424907"]},{"id":"https://openalex.org/I2279609970","display_name":"Universit\u00e9 de Lille","ror":"https://ror.org/02kzqn938","country_code":"FR","type":"education","lineage":["https://openalex.org/I2279609970"]},{"id":"https://openalex.org/I4210115519","display_name":"Centre de Recherche en Informatique","ror":"https://ror.org/020cdve92","country_code":"FR","type":"facility","lineage":["https://openalex.org/I190752583","https://openalex.org/I2746051580","https://openalex.org/I4210091621","https://openalex.org/I4210115519","https://openalex.org/I70768539"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"P. Devienne","raw_affiliation_strings":["Laboratoire d'Informatique Fondamentale de Lille, France","CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 (Universit\u00e9 de Lille - Campus scientifique - B\u00e2timent ESPRIT - Avenue Henri Poincar\u00e9 - 59655 Villeneuve d\u2019Ascq - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'Informatique Fondamentale de Lille, France","institution_ids":["https://openalex.org/I174424907"]},{"raw_affiliation_string":"CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 (Universit\u00e9 de Lille - Campus scientifique - B\u00e2timent ESPRIT - Avenue Henri Poincar\u00e9 - 59655 Villeneuve d\u2019Ascq - France)","institution_ids":["https://openalex.org/I4210115519","https://openalex.org/I2279609970"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080756796","display_name":"Sophie Tison","orcid":"https://orcid.org/0000-0002-8426-6230"},"institutions":[{"id":"https://openalex.org/I174424907","display_name":"Laboratoire d'Informatique Fondamentale de Lille","ror":"https://ror.org/05rhg0h08","country_code":"FR","type":"facility","lineage":["https://openalex.org/I174424907"]},{"id":"https://openalex.org/I2279609970","display_name":"Universit\u00e9 de Lille","ror":"https://ror.org/02kzqn938","country_code":"FR","type":"education","lineage":["https://openalex.org/I2279609970"]},{"id":"https://openalex.org/I4210115519","display_name":"Centre de Recherche en Informatique","ror":"https://ror.org/020cdve92","country_code":"FR","type":"facility","lineage":["https://openalex.org/I190752583","https://openalex.org/I2746051580","https://openalex.org/I4210091621","https://openalex.org/I4210115519","https://openalex.org/I70768539"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"S. Tison","raw_affiliation_strings":["Laboratoire d'Informatique Fondamentale de Lille, France","CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 (Universit\u00e9 de Lille - Campus scientifique - B\u00e2timent ESPRIT - Avenue Henri Poincar\u00e9 - 59655 Villeneuve d\u2019Ascq - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'Informatique Fondamentale de Lille, France","institution_ids":["https://openalex.org/I174424907"]},{"raw_affiliation_string":"CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 (Universit\u00e9 de Lille - Campus scientifique - B\u00e2timent ESPRIT - Avenue Henri Poincar\u00e9 - 59655 Villeneuve d\u2019Ascq - France)","institution_ids":["https://openalex.org/I4210115519","https://openalex.org/I2279609970"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112223771","display_name":"J.-L. Boulanger","orcid":null},"institutions":[{"id":"https://openalex.org/I102516824","display_name":"Universit\u00e9 de Technologie de Compi\u00e8gne","ror":"https://ror.org/04y5kwa70","country_code":"FR","type":"education","lineage":["https://openalex.org/I102516824"]},{"id":"https://openalex.org/I4210088387","display_name":"Heuristics and Diagnostics for Complex Systems","ror":"https://ror.org/0075hvk77","country_code":"FR","type":"facility","lineage":["https://openalex.org/I102516824","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210088387","https://openalex.org/I4210159245"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J.-L. Boulanger","raw_affiliation_strings":["Heudiasyc, Universit\u00e9 de Compiagne, France","Heudiasyc - Heuristique et Diagnostic des Syst\u00e8mes Complexes [Compi\u00e8gne] (UTC, CS 60319 - 57 avenue de Landshut - 60203 Compi\u00e8gne cedex - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Heudiasyc, Universit\u00e9 de Compiagne, France","institution_ids":["https://openalex.org/I4210088387"]},{"raw_affiliation_string":"Heudiasyc - Heuristique et Diagnostic des Syst\u00e8mes Complexes [Compi\u00e8gne] (UTC, CS 60319 - 57 avenue de Landshut - 60203 Compi\u00e8gne cedex - France)","institution_ids":["https://openalex.org/I4210088387","https://openalex.org/I102516824"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003352943","display_name":"Georges Mariano","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087884","display_name":"H\u00f4pital Louis-Mourier","ror":"https://ror.org/004nnf780","country_code":"FR","type":"healthcare","lineage":["https://openalex.org/I4210087884","https://openalex.org/I4210097159"]},{"id":"https://openalex.org/I4210097159","display_name":"Assistance Publique \u2013 H\u00f4pitaux de Paris","ror":"https://ror.org/00pg5jh14","country_code":"FR","type":"healthcare","lineage":["https://openalex.org/I4210097159"]},{"id":"https://openalex.org/I85905123","display_name":"Institut National de Recherche et de S\u00e9curit\u00e9","ror":"https://ror.org/01dg85j68","country_code":"FR","type":"funder","lineage":["https://openalex.org/I85905123"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"G. Mariano","raw_affiliation_strings":["Institut National de Recherche sur les Transports et leur S\u00e9curit\u00e9, France","H\u00f4pital Louis Mourier - AP-HP [Colombes] (178 Rue des Renouillers, 92700 Colombes - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institut National de Recherche sur les Transports et leur S\u00e9curit\u00e9, France","institution_ids":["https://openalex.org/I85905123"]},{"raw_affiliation_string":"H\u00f4pital Louis Mourier - AP-HP [Colombes] (178 Rue des Renouillers, 92700 Colombes - France)","institution_ids":["https://openalex.org/I4210087884","https://openalex.org/I4210097159"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5034230117"],"corresponding_institution_ids":["https://openalex.org/I174424907","https://openalex.org/I2279609970","https://openalex.org/I44563897"],"apc_list":null,"apc_paid":null,"fwci":0.7949,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.72816127,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"241","last_page":"242"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8448834419250488},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7898057699203491},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.697162926197052},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6463401317596436},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6430397033691406},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5582425594329834},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5353164672851562},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4952467978000641},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4516828954219818},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.4402751326560974},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.4239698648452759},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.36459702253341675},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3489713668823242},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.3440643548965454},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.31081509590148926},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.20774757862091064},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15643396973609924},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.12745711207389832},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1140953004360199},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09697297215461731}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8448834419250488},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7898057699203491},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.697162926197052},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6463401317596436},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6430397033691406},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5582425594329834},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5353164672851562},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4952467978000641},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4516828954219818},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.4402751326560974},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.4239698648452759},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.36459702253341675},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3489713668823242},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.3440643548965454},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.31081509590148926},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20774757862091064},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15643396973609924},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.12745711207389832},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1140953004360199},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09697297215461731},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/csd.2003.1207723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/csd.2003.1207723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.2.5728","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.2.5728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.chez.com/bjlressources/Publication/ACSD2003-BHDL/ACSD2003f.ps","raw_type":"text"},{"id":"pmh:oai:HAL:hal-03526474v1","is_oa":false,"landing_page_url":"https://univ-artois.hal.science/hal-03526474","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"International Conference on Application of Concurrency to System Design (ACSD'2003), 2003, Guimaraes, France. pp.241-242, &#x27E8;10.1109/csd.2003.1207723&#x27E9;","raw_type":"Conference papers"},{"id":"pmh:oai:HAL:hal-04490747v1","is_oa":false,"landing_page_url":"https://hal.science/hal-04490747","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"International Conference on Application of Concurrency to System Design (ACSD'2003), Jun 2003, Guimaraes, Portugal. IEEE Comput. Soc, pp.241-242, 2003, 0-7695-1887-7. &#x27E8;10.1109/CSD.2003.1207723&#x27E9;","raw_type":"Proceedings"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1559870885","https://openalex.org/W1598579619","https://openalex.org/W4254354208","https://openalex.org/W6635615470"],"related_works":["https://openalex.org/W2376028644","https://openalex.org/W2141004294","https://openalex.org/W1605062719","https://openalex.org/W2091329789","https://openalex.org/W2895905110","https://openalex.org/W2363829830","https://openalex.org/W2039193071","https://openalex.org/W35543821","https://openalex.org/W2051291427","https://openalex.org/W2253173388"],"abstract_inverted_index":{"The":[0],"main":[1],"goal":[2],"of":[3,11,14,21,26,32],"this":[4,58],"project":[5,59],"is":[6,52],"to":[7],"provide":[8],"a":[9,41,61,66],"method":[10,34],"correct":[12,38],"design":[13,39,48],"digital":[15],"circuit.":[16],"It":[17],"combines":[18],"the":[19,23,30,37,47],"advantages":[20],"VHDL,":[22],"well-known":[24],"language":[25],"circuit":[27],"design,":[28],"with":[29,65],"power":[31],"B":[33],"that":[35],"guarantees":[36],"(w.r.t.":[40],"formal":[42],"specification).":[43],"This":[44],"allows":[45],"avoiding":[46],"test":[49],"since":[50],"it":[51],"\"correct":[53],"by":[54],"proven":[55],"construction\".":[56],"Furthermore,":[57],"provides":[60],"tool,":[62],"called":[63],"BHDL,":[64],"graphical":[67],"interface":[68],"for":[69],"creating,":[70],"editing,":[71],"viewing":[72],"and":[73],"proving":[74],"modular":[75],"hardware":[76],"architectures.":[77]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-05-07T13:39:58.223016","created_date":"2025-10-10T00:00:00"}
