{"id":"https://openalex.org/W4376605534","doi":"https://doi.org/10.1109/coolchips57690.2023.10122025","title":"FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System","display_name":"FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System","publication_year":2023,"publication_date":"2023-04-19","ids":{"openalex":"https://openalex.org/W4376605534","doi":"https://doi.org/10.1109/coolchips57690.2023.10122025"},"language":"en","primary_location":{"id":"doi:10.1109/coolchips57690.2023.10122025","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/coolchips57690.2023.10122025","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108620860","display_name":"Takeshi Ohkawa","orcid":"https://orcid.org/0000-0002-6536-6439"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Takeshi Ohkawa","raw_affiliation_strings":["Kumamoto University,Kumamoto,Japan,860-8555"],"affiliations":[{"raw_affiliation_string":"Kumamoto University,Kumamoto,Japan,860-8555","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061495708","display_name":"Masahiro Aoyagi","orcid":"https://orcid.org/0000-0002-8145-5909"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Aoyagi","raw_affiliation_strings":["Kumamoto University,Kumamoto,Japan,860-8555"],"affiliations":[{"raw_affiliation_string":"Kumamoto University,Kumamoto,Japan,860-8555","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108620860"],"corresponding_institution_ids":["https://openalex.org/I96036126"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.03854139,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.8246607184410095},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7836816310882568},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7164486050605774},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6409400701522827},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5771051049232483},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.513983428478241},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43031683564186096},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4293524920940399},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.4242570698261261},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.4161011278629303},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36780300736427307},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.2940843105316162},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.20513397455215454}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.8246607184410095},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7836816310882568},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7164486050605774},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6409400701522827},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5771051049232483},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.513983428478241},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43031683564186096},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4293524920940399},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.4242570698261261},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.4161011278629303},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36780300736427307},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.2940843105316162},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.20513397455215454},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/coolchips57690.2023.10122025","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/coolchips57690.2023.10122025","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8100000023841858,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1985562453","https://openalex.org/W2094727347","https://openalex.org/W2154194029","https://openalex.org/W2742121483","https://openalex.org/W2794754353","https://openalex.org/W4242435189","https://openalex.org/W4299418822"],"related_works":["https://openalex.org/W2388672758","https://openalex.org/W2135981148","https://openalex.org/W2754086592","https://openalex.org/W2144357574","https://openalex.org/W2065289416","https://openalex.org/W3198758847","https://openalex.org/W4230458348","https://openalex.org/W1966325333","https://openalex.org/W1581055755","https://openalex.org/W2519428907"],"abstract_inverted_index":{"Through-Silicon-Via":[0],"(TSV)":[1],"is":[2,17,39,83,116],"expected":[3],"to":[4,41,72,98,118],"realize":[5],"high-performance,":[6],"low-power":[7],"consumption,":[8],"and":[9,101],"lowcost":[10],"3D-LSI":[11],"(Large":[12],"Scale":[13],"Integration)":[14],"system.":[15],"It":[16],"realized":[18],"by":[19],"integrating":[20],"pre-manufactured":[21],"chips":[22,100,105],"with":[23],"a":[24,32,43,84],"3D":[25],"Standard":[26],"Chip":[27],"Stacking":[28],"System":[29],"(3D-SCSS)":[30],"through":[31],"standard":[33,44],"bus":[34],"TSV":[35,56,126],"connection.":[36],"However,":[37],"it":[38],"difficult":[40],"define":[42],"chip":[45],"connection":[46],"mechanism.":[47],"This":[48],"paper":[49],"proposes":[50],"an":[51],"FPGA":[52],"emulation":[53,114],"of":[54,63,76,123],"the":[55,61,74,79,104,107,113,120,124],"dataflow":[57,90,127],"network":[58],"for":[59],"evaluating":[60],"performance":[62,122],"3D-SCSS.":[64,108],"To":[65],"emulate":[66],"3D-SCSS,":[67],"multiple-clock":[68],"domains":[69],"are":[70,92,96],"assumed":[71],"overcome":[73],"problem":[75],"jitter":[77],"in":[78,106],"global":[80],"clock,":[81],"which":[82],"separated":[85],"clock":[86],"domain":[87],"model.":[88],"Simple":[89],"experiments":[91],"done":[93],"where":[94],"processes":[95],"deployed":[97],"different":[99],"communicate":[102],"among":[103],"The":[109],"evaluation":[110],"shows":[111],"that":[112],"method":[115],"suitable":[117],"measure":[119],"latency":[121],"proposed":[125],"network.":[128],"(Keywords:":[129],"3D-LSI,":[130],"TSV,":[131],"FPGA,":[132],"Emulation,":[133],"Dataflow,":[134],"3D-SCSS)":[135]},"counts_by_year":[],"updated_date":"2025-12-24T23:09:58.560324","created_date":"2025-10-10T00:00:00"}