{"id":"https://openalex.org/W3026838713","doi":"https://doi.org/10.1109/coolchips49199.2020.9097643","title":"Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture","display_name":"Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture","publication_year":2020,"publication_date":"2020-04-01","ids":{"openalex":"https://openalex.org/W3026838713","doi":"https://doi.org/10.1109/coolchips49199.2020.9097643","mag":"3026838713"},"language":"en","primary_location":{"id":"doi:10.1109/coolchips49199.2020.9097643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/coolchips49199.2020.9097643","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069374897","display_name":"Masayuki Sato","orcid":"https://orcid.org/0000-0002-4186-5014"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masayuki Sato","raw_affiliation_strings":["Graduate School of Information Sciences, Tohoku University, Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, Tohoku University, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100337759","display_name":"Hao Xue","orcid":"https://orcid.org/0009-0004-0448-2497"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Xue Hao","raw_affiliation_strings":["Graduate School of Information Sciences, Tohoku University, Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, Tohoku University, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051997684","display_name":"Kazuhiko Komatsu","orcid":"https://orcid.org/0000-0003-4463-8359"},"institutions":[{"id":"https://openalex.org/I4210093896","display_name":"Tohoku University Hospital","ror":"https://ror.org/00kcd6x60","country_code":"JP","type":"healthcare","lineage":["https://openalex.org/I4210093896"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuhiko Komatsu","raw_affiliation_strings":["Cyberscience Center, Tohoku University, Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cyberscience Center, Tohoku University, Sendai, Japan","institution_ids":["https://openalex.org/I4210093896"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007893254","display_name":"Hiroaki Kobayashi","orcid":"https://orcid.org/0000-0002-3350-1413"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroaki Kobayashi","raw_affiliation_strings":["Graduate School of Information Sciences, Tohoku University, Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, Tohoku University, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.818953812122345},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7595935463905334},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.6664944291114807},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6009414792060852},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5725717544555664},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5238739848136902},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.48274511098861694},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4518340528011322},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.43376994132995605},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.4303734302520752},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4203781485557556},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3739399313926697},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27218568325042725},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12577980756759644},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.059596896171569824}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.818953812122345},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7595935463905334},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.6664944291114807},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6009414792060852},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5725717544555664},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5238739848136902},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.48274511098861694},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4518340528011322},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.43376994132995605},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.4303734302520752},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4203781485557556},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3739399313926697},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27218568325042725},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12577980756759644},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.059596896171569824},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/coolchips49199.2020.9097643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/coolchips49199.2020.9097643","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2108048675","https://openalex.org/W2255015856","https://openalex.org/W2803074168"],"related_works":["https://openalex.org/W2147122795","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W2167303720","https://openalex.org/W2268996566","https://openalex.org/W2109715593","https://openalex.org/W3161817247","https://openalex.org/W2012518269","https://openalex.org/W2068309140","https://openalex.org/W4239937081"],"abstract_inverted_index":{"The":[0,38,60,79],"capacity":[1],"and":[2,26,87,98],"the":[3,7,31,54,64,68,72,76,84,93,100],"energy":[4,94],"consumption":[5,95],"of":[6,43,46,56,67],"last-level":[8],"cache":[9,23],"(LLC)":[10],"must":[11],"be":[12],"improved":[13],"toward":[14],"future":[15],"microprocessors.":[16],"This":[17],"paper":[18],"proposes":[19],"an":[20],"STT-RAM-based":[21],"hybrid":[22],"architecture":[24],"(HCA)":[25],"its":[27,88],"replacement":[28],"policy,":[29],"named":[30],"Fast":[32],"Region":[33],"First":[34],"Used":[35],"(FRFU)":[36],"policy.":[37,78],"proposed":[39,73,85],"HCA":[40,74,86],"is":[41],"composed":[42],"two":[44],"types":[45],"STT-RAM":[47,58],"devices":[48],"with":[49,107],"different":[50],"characteristics":[51],"to":[52],"mitigate":[53],"disadvantages":[55],"non-volatile":[57],"devices.":[59],"FRFU":[61],"policy":[62,89],"provides":[63],"better":[65],"handling":[66],"data":[69],"blocks":[70],"for":[71],"than":[75],"LRU":[77],"evaluation":[80],"results":[81],"show":[82],"that":[83],"can":[90],"successfully":[91],"reduce":[92],"by":[96,102],"55%":[97],"improve":[99],"performance":[101],"1%":[103],"on":[104],"average":[105],"compared":[106],"a":[108],"conventional":[109],"SRAM":[110],"LLC.":[111]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
