{"id":"https://openalex.org/W2148074001","doi":"https://doi.org/10.1109/coolchips.2012.6216585","title":"Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation","display_name":"Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2148074001","doi":"https://doi.org/10.1109/coolchips.2012.6216585","mag":"2148074001"},"language":"en","primary_location":{"id":"doi:10.1109/coolchips.2012.6216585","is_oa":false,"landing_page_url":"https://doi.org/10.1109/coolchips.2012.6216585","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE COOL Chips XV","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085875405","display_name":"Benjamin Devlin","orcid":"https://orcid.org/0009-0008-2823-549X"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Benjamin Devlin","raw_affiliation_strings":["Dept. of Electronic Engineering, University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronic Engineering, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["VLSI Design and Education Center(VDEC), University of Tokyo, Bunkyo-ku, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center(VDEC), University of Tokyo, Bunkyo-ku, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["VLSI Design and Education Center(VDEC), University of Tokyo, Bunkyo-ku, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center(VDEC), University of Tokyo, Bunkyo-ku, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.8128246665000916},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.7526916861534119},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5707629323005676},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.554640531539917},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.5368369817733765},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5342480540275574},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5294496417045593},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49581488966941833},{"id":"https://openalex.org/keywords/input-offset-voltage","display_name":"Input offset voltage","score":0.49191975593566895},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.4792649447917938},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43488454818725586},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43058595061302185},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.333305299282074},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.26302558183670044},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23562517762184143},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22948595881462097},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.07764366269111633}],"concepts":[{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.8128246665000916},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.7526916861534119},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5707629323005676},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.554640531539917},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.5368369817733765},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5342480540275574},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5294496417045593},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49581488966941833},{"id":"https://openalex.org/C63651839","wikidata":"https://www.wikidata.org/wiki/Q478566","display_name":"Input offset voltage","level":5,"score":0.49191975593566895},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.4792649447917938},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43488454818725586},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43058595061302185},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.333305299282074},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.26302558183670044},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23562517762184143},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22948595881462097},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.07764366269111633},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/coolchips.2012.6216585","is_oa":false,"landing_page_url":"https://doi.org/10.1109/coolchips.2012.6216585","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE COOL Chips XV","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1989227777","https://openalex.org/W1999051983","https://openalex.org/W2117956094","https://openalex.org/W2138724413","https://openalex.org/W2168559772","https://openalex.org/W3145439752"],"related_works":["https://openalex.org/W2951387119","https://openalex.org/W2913250844","https://openalex.org/W2472717445","https://openalex.org/W2065257009","https://openalex.org/W2580309824","https://openalex.org/W2135250276","https://openalex.org/W1618072219","https://openalex.org/W2968761826","https://openalex.org/W2137342431","https://openalex.org/W2551379717"],"abstract_inverted_index":{"We":[0,26],"present":[1,27],"a":[2,36,78],"low":[3],"overhead":[4],"technique":[5,33],"that":[6,42,62],"can":[7,57],"be":[8],"used":[9],"to":[10,35,49,67,75],"offset":[11,58],"both":[12],"large":[13,64],"systematic":[14],"and":[15],"random":[16],"process":[17],"delay":[18,65],"variation":[19],"in":[20],"the":[21],"near-threshold":[22],"voltage":[23,54],"operation":[24,46,72],"region.":[25],"an":[28],"analysis":[29],"of":[30,45,73],"this":[31,32],"applied":[34],"65nm":[37],"CMOS":[38],"self":[39],"synchronous":[40],"FPGA":[41],"is":[43],"capable":[44],"from":[47],"2.0V":[48],"0.37V.":[50],"By":[51],"using":[52],"dual":[53],"supplies,":[55],"we":[56],"gate-level":[59],"pipeline":[60],"stages":[61],"show":[63],"variation,":[66],"achieve":[68],"energy":[69],"savings":[70],"per":[71],"up":[74],"102x":[76],"for":[77],"200":[79],"stage":[80],"pipeline.":[81]},"counts_by_year":[{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}