{"id":"https://openalex.org/W2098537124","doi":"https://doi.org/10.1109/conect.2002.1039258","title":"Scalability port: a coherent interface for shared memory multiprocessors","display_name":"Scalability port: a coherent interface for shared memory multiprocessors","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2098537124","doi":"https://doi.org/10.1109/conect.2002.1039258","mag":"2098537124"},"language":"en","primary_location":{"id":"doi:10.1109/conect.2002.1039258","is_oa":false,"landing_page_url":"https://doi.org/10.1109/conect.2002.1039258","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 10th Symposium on High Performance Interconnects","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066664814","display_name":"Mani Azimi","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M. Azimi","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020889951","display_name":"Fay\u00e9 A. Briggs","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. Briggs","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084339319","display_name":"M. Cekleov","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Cekleov","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023572343","display_name":"M. Khare","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Khare","raw_affiliation_strings":["Intel Corp., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081266273","display_name":"Akhilesh Kumar","orcid":"https://orcid.org/0000-0002-0141-6388"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Kumar","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043345576","display_name":"Lily Pao Looi","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L.P. Looi","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5066664814"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.4929,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.86556376,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"65","last_page":"70"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8255031108856201},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5794271230697632},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.56940096616745},{"id":"https://openalex.org/keywords/chipset","display_name":"Chipset","score":0.567866861820221},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4693656265735626},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4421829283237457},{"id":"https://openalex.org/keywords/physical-layer","display_name":"Physical layer","score":0.42766445875167847},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.42685556411743164},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.4256308674812317},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4110245406627655},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.34949803352355957},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3203030824661255},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.3135104775428772},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.10946938395500183},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.0862017571926117}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8255031108856201},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5794271230697632},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.56940096616745},{"id":"https://openalex.org/C73431340","wikidata":"https://www.wikidata.org/wiki/Q182656","display_name":"Chipset","level":3,"score":0.567866861820221},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4693656265735626},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4421829283237457},{"id":"https://openalex.org/C19247436","wikidata":"https://www.wikidata.org/wiki/Q192727","display_name":"Physical layer","level":3,"score":0.42766445875167847},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.42685556411743164},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.4256308674812317},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4110245406627655},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.34949803352355957},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3203030824661255},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.3135104775428772},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.10946938395500183},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.0862017571926117},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/conect.2002.1039258","is_oa":false,"landing_page_url":"https://doi.org/10.1109/conect.2002.1039258","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 10th Symposium on High Performance Interconnects","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7099999785423279}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337392","display_name":"Division of Electrical, Communications and Cyber Systems","ror":"https://ror.org/01krpsy48"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2044643398","https://openalex.org/W2082225037","https://openalex.org/W2101195691","https://openalex.org/W2104674486","https://openalex.org/W2462193902","https://openalex.org/W6675267351"],"related_works":["https://openalex.org/W4285204597","https://openalex.org/W2290195868","https://openalex.org/W3193874149","https://openalex.org/W1482370651","https://openalex.org/W2407815036","https://openalex.org/W2118508246","https://openalex.org/W4255008187","https://openalex.org/W2079555365","https://openalex.org/W2135302104","https://openalex.org/W276034605"],"abstract_inverted_index":{"The":[0,16,35,51,64,79],"scalability":[1],"port":[2],"(SP)":[3],"is":[4,86],"a":[5],"point-to-point":[6],"cache":[7,68],"consistent":[8],"interface":[9,18,85],"to":[10],"build":[11],"scalable":[12],"shared":[13],"memory":[14],"multiprocessors.":[15],"SP":[17,84],"consists":[19],"of":[20,23,82,106],"three":[21],"layers":[22],"abstraction:":[24],"the":[25,28,32,83,88,97,107],"physical":[26,36],"layer,":[27],"link":[29,52],"layer":[30,37,53,66],"and":[31,43,57,61,73,93,103],"protocol":[33,65],"layer.":[34],"uses":[38],"pin-efficient":[39],"simultaneous":[40],"bi-directional":[41],"signaling":[42],"operates":[44],"at":[45],"800":[46],"MHz":[47],"in":[48,87],"each":[49],"direction.":[50],"supports":[54],"virtual":[55],"channels":[56],"provides":[58],"flow":[59],"control":[60],"reliable":[62],"transmission.":[63],"implements":[67],"consistency,":[69,71],"TLB":[70],"synchronization,":[72],"interrupt":[74],"delivery":[75],"functions":[76],"among":[77],"others.":[78],"first":[80],"implementation":[81],"Intel/sup":[89],"/spl":[90,100],"reg//":[91],"E8870":[92],"E9870":[94],"chipset":[95],"for":[96],"Intel":[98],"Itanium/sup":[99],"reg//2":[101],"processor":[102,109],"future":[104],"generations":[105],"Itanium":[108],"family.":[110]},"counts_by_year":[],"updated_date":"2026-03-14T08:43:22.919905","created_date":"2025-10-10T00:00:00"}