{"id":"https://openalex.org/W2811132583","doi":"https://doi.org/10.1109/codit.2018.8394842","title":"FPGA Master based on chip communications architecture for Cyclone V SoC running Linux","display_name":"FPGA Master based on chip communications architecture for Cyclone V SoC running Linux","publication_year":2018,"publication_date":"2018-04-01","ids":{"openalex":"https://openalex.org/W2811132583","doi":"https://doi.org/10.1109/codit.2018.8394842","mag":"2811132583"},"language":"en","primary_location":{"id":"doi:10.1109/codit.2018.8394842","is_oa":false,"landing_page_url":"https://doi.org/10.1109/codit.2018.8394842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 5th International Conference on Control, Decision and Information Technologies (CoDIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077287127","display_name":"Rihards Novickis","orcid":"https://orcid.org/0000-0001-8585-1821"},"institutions":[{"id":"https://openalex.org/I4210162447","display_name":"Institute of Electronics and Computer Science","ror":"https://ror.org/05bsp2531","country_code":"LV","type":"facility","lineage":["https://openalex.org/I4210162447","https://openalex.org/I70055295"]}],"countries":["LV"],"is_corresponding":true,"raw_author_name":"Rihards Novickis","raw_affiliation_strings":["Institute of Electronics and Computer Science, Riga, Latvia"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics and Computer Science, Riga, Latvia","institution_ids":["https://openalex.org/I4210162447"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072892931","display_name":"Modris Greit\u0101ns","orcid":"https://orcid.org/0000-0002-5405-0738"},"institutions":[{"id":"https://openalex.org/I4210162447","display_name":"Institute of Electronics and Computer Science","ror":"https://ror.org/05bsp2531","country_code":"LV","type":"facility","lineage":["https://openalex.org/I4210162447","https://openalex.org/I70055295"]}],"countries":["LV"],"is_corresponding":false,"raw_author_name":"Modris Greitans","raw_affiliation_strings":["Institute of Electronics and Computer Science, Riga, Latvia"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics and Computer Science, Riga, Latvia","institution_ids":["https://openalex.org/I4210162447"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5077287127"],"corresponding_institution_ids":["https://openalex.org/I4210162447"],"apc_list":null,"apc_paid":null,"fwci":0.5049,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.60804204,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"403","last_page":"408"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7268521785736084},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7104756832122803},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5637905597686768},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4658891260623932},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4013594090938568},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3573119044303894},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32904380559921265}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7268521785736084},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7104756832122803},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5637905597686768},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4658891260623932},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4013594090938568},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3573119044303894},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32904380559921265},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/codit.2018.8394842","is_oa":false,"landing_page_url":"https://doi.org/10.1109/codit.2018.8394842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 5th International Conference on Control, Decision and Information Technologies (CoDIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320327207","display_name":"Electronic Components and Systems for European Leadership","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1999941863","https://openalex.org/W2022020111","https://openalex.org/W2076089313","https://openalex.org/W2105011467","https://openalex.org/W2111138632","https://openalex.org/W2171053899","https://openalex.org/W2281395449","https://openalex.org/W2315613604","https://openalex.org/W2586506467","https://openalex.org/W2785412206"],"related_works":["https://openalex.org/W2378211422","https://openalex.org/W4321353415","https://openalex.org/W2130974462","https://openalex.org/W972276598","https://openalex.org/W2086519370","https://openalex.org/W2028665553","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882"],"abstract_inverted_index":{"The":[0],"emergence":[1],"of":[2,20,53,105,162],"Field":[3],"Programmable":[4],"System":[5],"on":[6],"Chip":[7],"(FPSoC)":[8],"technology":[9],"potentially":[10],"provides":[11],"significant":[12],"advantages":[13,52],"for":[14,114,123,129],"computationally":[15],"intense":[16],"tasks.":[17],"Deep":[18],"understanding":[19],"hardware":[21],"and":[22,85,101,120,133,156],"software":[23,41],"design":[24],"paradigms":[25],"is":[26,60,117],"necessary":[27],"to":[28,93,158],"create":[29],"successful":[30],"system's":[31,54],"architecture,":[32],"this":[33,64],"task":[34],"can":[35],"become":[36],"even":[37],"more":[38],"challenging":[39],"if":[40],"part":[42],"adopts":[43],"operating":[44],"system":[45],"with":[46,100],"memory":[47,74,116,135],"virtualization.":[48],"When":[49],"exploiting":[50],"potential":[51],"dual":[55],"nature,":[56],"an":[57],"important":[58],"topic":[59],"chip-level":[61],"communications.":[62],"In":[63],"article,":[65],"authors":[66],"target":[67],"Altera":[68],"Cyclone":[69,152],"V":[70,153],"SoC":[71,154],"devices,":[72],"address":[73],"non-continuity":[75],"in":[76],"Linux,":[77],"develop":[78],"FPGA":[79,130,147],"master":[80,131,148],"based":[81,164],"on-chip":[82],"communications":[83],"architecture":[84],"benchmark":[86],"different":[87],"communication":[88],"scenarios":[89],"-":[90],"direct":[91],"connection":[92,96],"SDRAM":[94],"interface,":[95],"via":[97],"Level-3":[98],"interconnect":[99],"without":[102],"the":[103],"utilization":[104],"Accelerator":[106],"Coherency":[107],"Port.":[108],"Maximum":[109],"achieved":[110],"simultaneous":[111],"read/write":[112],"throughput":[113],"non-cached":[115],"20.08":[118],"Gbps":[119,122],"11.26":[121],"cached":[124],"memory.":[125],"Developed":[126],"Linux":[127,163],"modules":[128],"control":[132],"contiguous":[134],"allocation":[136],"are":[137],"provided":[138],"as":[139],"open":[140],"source":[141],"software.":[142],"This":[143],"work":[144],"represents":[145],"detailed":[146],"communication's":[149],"analysis":[150],"targeting":[151],"devices":[155],"aspires":[157],"accelerate":[159],"development":[160],"process":[161],"FPSoC":[165],"projects.":[166]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}