{"id":"https://openalex.org/W2770705511","doi":"https://doi.org/10.1109/codit.2017.8102748","title":"Hardware implementation of efficient path reconstruction for the Smith-Waterman algorithm","display_name":"Hardware implementation of efficient path reconstruction for the Smith-Waterman algorithm","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2770705511","doi":"https://doi.org/10.1109/codit.2017.8102748","mag":"2770705511"},"language":"en","primary_location":{"id":"doi:10.1109/codit.2017.8102748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/codit.2017.8102748","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 4th International Conference on Control, Decision and Information Technologies (CoDIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://www.um.edu.mt/library/oar/handle/123456789/58997","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110808017","display_name":"Karl Buhagiar","orcid":null},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":true,"raw_author_name":"Karl Buhagiar","raw_affiliation_strings":["Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044810941","display_name":"Owen Casha","orcid":"https://orcid.org/0000-0002-4337-5609"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Owen Casha","raw_affiliation_strings":["Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033957295","display_name":"Ivan Grech","orcid":"https://orcid.org/0000-0002-3721-0015"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Ivan Grech","raw_affiliation_strings":["Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051783142","display_name":"Edward Gatt","orcid":"https://orcid.org/0000-0001-6879-719X"},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Edward Gatt","raw_affiliation_strings":["Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110698610","display_name":"Joseph Micallef","orcid":null},"institutions":[{"id":"https://openalex.org/I197854408","display_name":"University of Malta","ror":"https://ror.org/03a62bv60","country_code":"MT","type":"education","lineage":["https://openalex.org/I197854408"]}],"countries":["MT"],"is_corresponding":false,"raw_author_name":"Joseph Micallef","raw_affiliation_strings":["Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Nanoelectronics, University of Malta, Msida, Malta","institution_ids":["https://openalex.org/I197854408"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5110808017"],"corresponding_institution_ids":["https://openalex.org/I197854408"],"apc_list":null,"apc_paid":null,"fwci":0.2072,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.58613367,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1113","last_page":"1116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9836000204086304,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9836000204086304,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10305","display_name":"Power System Optimization and Stability","score":0.9714999794960022,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10346","display_name":"Magnetic confinement fusion research","score":0.9621999859809875,"subfield":{"id":"https://openalex.org/subfields/3106","display_name":"Nuclear and High Energy Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8457401394844055},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7674996256828308},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7003050446510315},{"id":"https://openalex.org/keywords/smith\u2013waterman-algorithm","display_name":"Smith\u2013Waterman algorithm","score":0.6157444715499878},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5789610743522644},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5658535957336426},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5292496085166931},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.5182254314422607},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.49621111154556274},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4851563572883606},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4174523651599884},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40338027477264404},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0809594988822937}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8457401394844055},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7674996256828308},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7003050446510315},{"id":"https://openalex.org/C72802188","wikidata":"https://www.wikidata.org/wiki/Q1683352","display_name":"Smith\u2013Waterman algorithm","level":5,"score":0.6157444715499878},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5789610743522644},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5658535957336426},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5292496085166931},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.5182254314422607},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.49621111154556274},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4851563572883606},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4174523651599884},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40338027477264404},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0809594988822937},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C45484198","wikidata":"https://www.wikidata.org/wiki/Q827246","display_name":"Sequence alignment","level":4,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C167625842","wikidata":"https://www.wikidata.org/wiki/Q899763","display_name":"Peptide sequence","level":3,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/codit.2017.8102748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/codit.2017.8102748","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 4th International Conference on Control, Decision and Information Technologies (CoDIT)","raw_type":"proceedings-article"},{"id":"pmh:oai:www.um.edu.mt:123456789/58997","is_oa":true,"landing_page_url":"https://www.um.edu.mt/library/oar/handle/123456789/58997","pdf_url":null,"source":{"id":"https://openalex.org/S4306400782","display_name":"OAR@UM (University of Malta)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I197854408","host_organization_name":"University of Malta","host_organization_lineage":["https://openalex.org/I197854408"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:www.um.edu.mt:123456789/58997","is_oa":true,"landing_page_url":"https://www.um.edu.mt/library/oar/handle/123456789/58997","pdf_url":null,"source":{"id":"https://openalex.org/S4306400782","display_name":"OAR@UM (University of Malta)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I197854408","host_organization_name":"University of Malta","host_organization_lineage":["https://openalex.org/I197854408"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1566539040","https://openalex.org/W2046220835","https://openalex.org/W2087064593","https://openalex.org/W2089610326"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W2364622490","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W4297665406","https://openalex.org/W2749962643","https://openalex.org/W2110818533","https://openalex.org/W2390807153","https://openalex.org/W1917852300","https://openalex.org/W2042515040"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,28,35,38,43,60,67,70,78,81,89],"hardware":[4,45],"implementation":[5,85],"of":[6,30,37,56,69,80,97,105,112],"a":[7,13,31,103,109],"differential":[8],"coded":[9],"Smith-Waterman":[10],"algorithm":[11,23,50],"on":[12,88],"field":[14],"programmable":[15],"gate":[16],"array":[17],"(FPGA).":[18],"A":[19],"novel":[20],"path":[21,61],"reconstruction":[22,62],"is":[24,51,63],"proposed":[25],"to":[26],"overcome":[27],"need":[29],"dedicated":[32],"memory":[33],"for":[34],"storage":[36],"similarity":[39,71],"matrix,":[40],"thus":[41],"limiting":[42],"on-chip":[44],"utilization.":[46],"In":[47],"addition,":[48],"this":[49],"also":[52],"efficient":[53],"in":[54,77],"terms":[55],"computational":[57],"speed":[58],"since":[59],"carried":[64],"out":[65],"during":[66],"computation":[68],"score,":[72],"rather":[73],"then":[74],"afterwards,":[75],"as":[76],"case":[79],"original":[82],"algorithm.":[83],"The":[84],"was":[86],"done":[87],"Xilinx":[90],"Spartan-6":[91],"XC6LX16-CS324":[92],"FPGA":[93],"using":[94],"VHDL,":[95],"consisting":[96],"1,024":[98],"processing":[99],"elements":[100],"and":[101],"exhibits":[102],"throughput":[104],"204.8":[106],"BCUPS":[107],"at":[108],"data":[110],"rate":[111],"600":[113],"Mbps.":[114]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}