{"id":"https://openalex.org/W7147086602","doi":"https://doi.org/10.1109/cnml68938.2026.11453181","title":"Design of FPGA Memory Architecture for Large-Scale Ad Hoc Network Simulation","display_name":"Design of FPGA Memory Architecture for Large-Scale Ad Hoc Network Simulation","publication_year":2026,"publication_date":"2026-01-30","ids":{"openalex":"https://openalex.org/W7147086602","doi":"https://doi.org/10.1109/cnml68938.2026.11453181"},"language":null,"primary_location":{"id":"doi:10.1109/cnml68938.2026.11453181","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cnml68938.2026.11453181","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 International Conference on Communication Networks and Machine Learning (CNML)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5123669690","display_name":"Xue Qin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210163363","display_name":"PLA Army Engineering University","ror":"https://ror.org/05mgp8x93","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210163363"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xue Qin","raw_affiliation_strings":["Army Engineering University of PLA,College of Communication Engineering,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Army Engineering University of PLA,College of Communication Engineering,Nanjing,China","institution_ids":["https://openalex.org/I4210163363"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5123711107","display_name":"Lufeng Qiao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210163363","display_name":"PLA Army Engineering University","ror":"https://ror.org/05mgp8x93","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210163363"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lufeng Qiao","raw_affiliation_strings":["Army Engineering University of PLA,College of Communication Engineering,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Army Engineering University of PLA,College of Communication Engineering,Nanjing,China","institution_ids":["https://openalex.org/I4210163363"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5123682378","display_name":"Zhanyou Du","orcid":null},"institutions":[{"id":"https://openalex.org/I4210163363","display_name":"PLA Army Engineering University","ror":"https://ror.org/05mgp8x93","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210163363"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhanyou Du","raw_affiliation_strings":["Army Engineering University of PLA,College of Communication Engineering,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Army Engineering University of PLA,College of Communication Engineering,Nanjing,China","institution_ids":["https://openalex.org/I4210163363"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5132608611","display_name":"Rongjian Li","orcid":null},"institutions":[{"id":"https://openalex.org/I4210163363","display_name":"PLA Army Engineering University","ror":"https://ror.org/05mgp8x93","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210163363"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Rongjian Li","raw_affiliation_strings":["Army Engineering University of PLA,College of Communication Engineering,Nanjing,China"],"affiliations":[{"raw_affiliation_string":"Army Engineering University of PLA,College of Communication Engineering,Nanjing,China","institution_ids":["https://openalex.org/I4210163363"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5123669690"],"corresponding_institution_ids":["https://openalex.org/I4210163363"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.94939759,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"61","last_page":"65"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.3546999990940094,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.3546999990940094,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10246","display_name":"Mobile Ad Hoc Networks","score":0.06949999928474426,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10138","display_name":"Network Traffic and Congestion Control","score":0.06040000170469284,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.498199999332428},{"id":"https://openalex.org/keywords/wireless-ad-hoc-network","display_name":"Wireless ad hoc network","score":0.4666000008583069},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.44929999113082886},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4327999949455261},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.4133000075817108},{"id":"https://openalex.org/keywords/random-access","display_name":"Random access","score":0.39430001378059387},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.39160001277923584},{"id":"https://openalex.org/keywords/computer-data-storage","display_name":"Computer data storage","score":0.3774999976158142},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.367000013589859}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8055999875068665},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.498199999332428},{"id":"https://openalex.org/C94523657","wikidata":"https://www.wikidata.org/wiki/Q4085781","display_name":"Wireless ad hoc network","level":3,"score":0.4666000008583069},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.44929999113082886},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4327999949455261},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.4133000075817108},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4133000075817108},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.39430001378059387},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.39160001277923584},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3898000121116638},{"id":"https://openalex.org/C194739806","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Computer data storage","level":2,"score":0.3774999976158142},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.367000013589859},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.36579999327659607},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3476000130176544},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.34619998931884766},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.335999995470047},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.33320000767707825},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.3330000042915344},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.32109999656677246},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.30730000138282776},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.3059000074863434},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.30149999260902405},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.2915000021457672},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28999999165534973},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.28279998898506165},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.27720001339912415},{"id":"https://openalex.org/C82687282","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Auxiliary memory","level":2,"score":0.26589998602867126},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2603999972343445},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.2599000036716461},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.2515999972820282},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.25060001015663147}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cnml68938.2026.11453181","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cnml68938.2026.11453181","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 International Conference on Communication Networks and Machine Learning (CNML)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1560111661","https://openalex.org/W2766390143","https://openalex.org/W2951619019","https://openalex.org/W3085088769","https://openalex.org/W3199481472","https://openalex.org/W4317418845","https://openalex.org/W4382204395","https://openalex.org/W4385452171","https://openalex.org/W4391183602","https://openalex.org/W4393066231","https://openalex.org/W4396710791","https://openalex.org/W4400526584","https://openalex.org/W4401110400","https://openalex.org/W4402593174","https://openalex.org/W4411799529","https://openalex.org/W4415594759"],"related_works":[],"abstract_inverted_index":{"To":[0],"address":[1],"data":[2,60],"storage":[3,48,96,109],"demands":[4],"in":[5],"large-scale":[6,98,119],"ad":[7,120],"hoc":[8,121],"network":[9,55,122],"simulations,":[10],"this":[11],"paper":[12],"designs":[13],"and":[14,62,115],"implements":[15],"a":[16,23,82,90,113],"hardware":[17],"buffer":[18],"management":[19],"system":[20,28],"based":[21],"on":[22,124],"heterogeneous":[24],"memory":[25,85,92],"architecture.":[26],"The":[27],"utilizes":[29],"Block":[30],"Random":[31,73],"Access":[32,74],"Memory":[33,75],"(BRAM)":[34],"within":[35],"the":[36,53,95,104],"Field":[37],"Programmable":[38],"Gate":[39],"Array":[40],"(FPGA)":[41],"as":[42,89],"first-level":[43],"memory,":[44],"allocating":[45],"independent":[46],"local":[47],"partitions":[49],"for":[50,118],"each":[51],"of":[52,97],"128":[54],"nodes":[56],"to":[57,80,93],"enable":[58],"rapid":[59],"access":[61],"isolated":[63],"management.":[64],"Concurrently,":[65],"off-":[66],"chip":[67],"Double":[68],"Data":[69],"Rate":[70],"Synchronous":[71],"Dynamic":[72],"(DDR":[76],"SDRAM)":[77],"is":[78],"employed":[79],"construct":[81],"high-capacity":[83],"shared":[84],"pool,":[86],"which":[87],"serves":[88],"second-level":[91],"support":[94],"data.":[99],"Simulation":[100],"results":[101],"demonstrate":[102],"that":[103],"design":[105],"successfully":[106],"achieves":[107],"effective":[108],"capacity":[110],"expansion,":[111],"providing":[112],"reliable":[114],"feasible":[116],"solution":[117],"simulations":[123],"resource-constrained":[125],"FPGA":[126],"platforms.":[127]},"counts_by_year":[],"updated_date":"2026-04-02T13:53:19.096889","created_date":"2026-04-02T00:00:00"}
