{"id":"https://openalex.org/W4412713372","doi":"https://doi.org/10.1109/civemsa65862.2025.11084817","title":"Accelerating Hardware Computational Speed-up of Digital Image Processing Algorithms using Flexible Tunable Multi-NIOS-II Soft Processors on an FPGA: A Centralized Versus a Distributed Solution","display_name":"Accelerating Hardware Computational Speed-up of Digital Image Processing Algorithms using Flexible Tunable Multi-NIOS-II Soft Processors on an FPGA: A Centralized Versus a Distributed Solution","publication_year":2025,"publication_date":"2025-06-12","ids":{"openalex":"https://openalex.org/W4412713372","doi":"https://doi.org/10.1109/civemsa65862.2025.11084817"},"language":"en","primary_location":{"id":"doi:10.1109/civemsa65862.2025.11084817","is_oa":false,"landing_page_url":"https://doi.org/10.1109/civemsa65862.2025.11084817","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications (CIVEMSA)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049432621","display_name":"Michael Levine","orcid":"https://orcid.org/0000-0001-7629-0081"},"institutions":[{"id":"https://openalex.org/I133738476","display_name":"University of Massachusetts Lowell","ror":"https://ror.org/03hamhx47","country_code":"US","type":"education","lineage":["https://openalex.org/I133738476"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Michael Levine","raw_affiliation_strings":["University of Massachusetts Lowell,CMINDS Research Center, Francis College of Engineering,Department of Electrical and Computer Engineering,Lowell,MA,USA,01854"],"affiliations":[{"raw_affiliation_string":"University of Massachusetts Lowell,CMINDS Research Center, Francis College of Engineering,Department of Electrical and Computer Engineering,Lowell,MA,USA,01854","institution_ids":["https://openalex.org/I133738476"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001646142","display_name":"Dalila B. Megherbi","orcid":"https://orcid.org/0000-0002-1282-597X"},"institutions":[{"id":"https://openalex.org/I133738476","display_name":"University of Massachusetts Lowell","ror":"https://ror.org/03hamhx47","country_code":"US","type":"education","lineage":["https://openalex.org/I133738476"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. B. Megherbi","raw_affiliation_strings":["University of Massachusetts Lowell,CMINDS Research Center, Francis College of Engineering,Department of Electrical and Computer Engineering,Lowell,MA,USA,01854"],"affiliations":[{"raw_affiliation_string":"University of Massachusetts Lowell,CMINDS Research Center, Francis College of Engineering,Department of Electrical and Computer Engineering,Lowell,MA,USA,01854","institution_ids":["https://openalex.org/I133738476"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5049432621"],"corresponding_institution_ids":["https://openalex.org/I133738476"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21010967,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8515410423278809},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7972205877304077},{"id":"https://openalex.org/keywords/nios-ii","display_name":"Nios II","score":0.6755535006523132},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4687115550041199},{"id":"https://openalex.org/keywords/digital-image-processing","display_name":"Digital image processing","score":0.42089617252349854},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.41713815927505493},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37765634059906006},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.36937570571899414},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3378511667251587},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3251674175262451},{"id":"https://openalex.org/keywords/computer-vision","display_name":"Computer vision","score":0.23231932520866394}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8515410423278809},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7972205877304077},{"id":"https://openalex.org/C2781190120","wikidata":"https://www.wikidata.org/wiki/Q438281","display_name":"Nios II","level":3,"score":0.6755535006523132},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4687115550041199},{"id":"https://openalex.org/C104317675","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Digital image processing","level":4,"score":0.42089617252349854},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.41713815927505493},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37765634059906006},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.36937570571899414},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3378511667251587},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3251674175262451},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.23231932520866394}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/civemsa65862.2025.11084817","is_oa":false,"landing_page_url":"https://doi.org/10.1109/civemsa65862.2025.11084817","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications (CIVEMSA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2091043420","https://openalex.org/W2552760595","https://openalex.org/W2558913450","https://openalex.org/W3037176692","https://openalex.org/W4206714816","https://openalex.org/W4247049820","https://openalex.org/W4391096042"],"related_works":["https://openalex.org/W2348913739","https://openalex.org/W3015372806","https://openalex.org/W2941415828","https://openalex.org/W2081985452","https://openalex.org/W2946438354","https://openalex.org/W1504972346","https://openalex.org/W4386504616","https://openalex.org/W1593730969","https://openalex.org/W2561491196","https://openalex.org/W2356087891"],"abstract_inverted_index":{"These":[0],"days,":[1],"there":[2],"is":[3,46,130,186],"a":[4,69,146,155,177,192,219,225],"big":[5],"wave":[6],"of":[7,77,85,97,125,128],"interest":[8,48],"in":[9,31,36,49,63,74,82,94,104,109,118,138,145,162,207],"the":[10,20,42,75,83,91,95,101,110,121,126,171,213],"search":[11],"for":[12,26,68,158],"efficient":[13],"algorithms":[14],"to":[15,136],"solve":[16],"many":[17],"problems":[18],"at":[19],"hardware":[21,50,156,189,205],"level":[22],"or":[23,57],"embedded":[24],"systems":[25],"measurements":[27],"and":[28,61,79,153,160,166,180,224,242,258],"computational":[29,80,214],"intelligence":[30],"image":[32,164],"processing":[33,165],"&":[34],"understanding":[35],"computer":[37],"vision,":[38],"as":[39,41],"well":[40],"life":[43],"sciences.":[44],"There":[45],"an":[47,139,208],"architectures":[51],"showing":[52],"how":[53],"FPGAs":[54,78,129],"can":[55,249],"compete":[56],"perhaps":[58,112],"outperform":[59],"GPUs":[60,86],"CPUs":[62],"some":[64,188],"applications.":[65],"Hardware":[66],"accelerators":[67],"CPU":[70],"provide":[71],"power":[72],"efficiency":[73],"case":[76,84,96],"performance":[81,215],"with":[87,187,198,203,230,245],"high":[88],"parallelism.":[89],"On":[90,120],"one":[92,124],"hand,":[93,123],"irregular":[98],"parallelism,":[99],"given":[100],"latest":[102],"development":[103,148],"FPGAs,":[105],"this":[106],"latter":[107],"may,":[108],"future,":[111],"exhibit":[113],"superiority":[114],"over":[115],"homogeneous":[116],"parallelism":[117],"GPUs.":[119],"other":[122],"limitations":[127],"that":[131],"they":[132],"are":[133],"relatively":[134],"\u201chard":[135],"program\u201d":[137],"optimized":[140],"RTL":[141],"code,":[142],"which":[143],"results":[144],"long":[147],"time.":[149],"This":[150,185],"paper":[151],"presents":[152],"evaluates":[154],"implementation":[157],"measurement":[159],"application":[161],"digital":[163],"understanding.":[167],"We":[168,210],"experimentally":[169,211],"show":[170],"further":[172],"speed-up":[173],"obtained":[174],"by":[175,253],"implementing":[176],"soft,":[178],"flexible,":[179],"heterogeneous":[181,226],"SoC":[182,222,228,240],"multi-core":[183,227],"architecture.":[184],"modification":[190],"via":[191],"synchronized":[193],"varying-size":[194],"multi-port":[195],"memory":[196],"access,":[197],"two":[199],"soft":[200,241],"NIOS-II":[201],"processors,":[202],"additional":[204,231,246],"modification,":[206],"FPGA.":[209],"measure":[212],"differences":[216],"between":[217],"using":[218],"centralized":[220],"software-programmable":[221],"approach":[223,229],"modified":[232,247],"hardware.":[233],"The":[234],"resulting":[235],"FPGA":[236],"system":[237],"methodology,":[238],"combining":[239,254],"flexible":[243],"components":[244],"hardware,":[248],"be":[250],"flexibly":[251],"programmed":[252],"assembly":[255],"language,":[256],"C/C++,":[257],"VHDL.":[259]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}