{"id":"https://openalex.org/W2105823147","doi":"https://doi.org/10.1109/ciss.2007.4298403","title":"An Attempt Towards Charge-Domain Logic (CDL)","display_name":"An Attempt Towards Charge-Domain Logic (CDL)","publication_year":2007,"publication_date":"2007-03-01","ids":{"openalex":"https://openalex.org/W2105823147","doi":"https://doi.org/10.1109/ciss.2007.4298403","mag":"2105823147"},"language":"en","primary_location":{"id":"doi:10.1109/ciss.2007.4298403","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ciss.2007.4298403","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 41st Annual Conference on Information Sciences and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110095689","display_name":"Koichi Itoh","orcid":null},"institutions":[{"id":"https://openalex.org/I149481174","display_name":"Tamagawa University","ror":"https://ror.org/05f8a4p63","country_code":"JP","type":"education","lineage":["https://openalex.org/I149481174"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Koichi Itoh","raw_affiliation_strings":["Department of Electronics Engineering, Tamagawa University, Machida, Tokyo, Japan","Tamagawa Univ., Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, Tamagawa University, Machida, Tokyo, Japan","institution_ids":["https://openalex.org/I149481174"]},{"raw_affiliation_string":"Tamagawa Univ., Tokyo","institution_ids":["https://openalex.org/I149481174"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010278982","display_name":"Masashi Yamazaki","orcid":"https://orcid.org/0000-0002-9293-3531"},"institutions":[{"id":"https://openalex.org/I149481174","display_name":"Tamagawa University","ror":"https://ror.org/05f8a4p63","country_code":"JP","type":"education","lineage":["https://openalex.org/I149481174"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masashi Yamazaki","raw_affiliation_strings":["Department of Electronics Engineering, Tamagawa University, Machida, Tokyo, Japan","Tamagawa Univ., Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, Tamagawa University, Machida, Tokyo, Japan","institution_ids":["https://openalex.org/I149481174"]},{"raw_affiliation_string":"Tamagawa Univ., Tokyo","institution_ids":["https://openalex.org/I149481174"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056237363","display_name":"Shinji Nakamura","orcid":null},"institutions":[{"id":"https://openalex.org/I149481174","display_name":"Tamagawa University","ror":"https://ror.org/05f8a4p63","country_code":"JP","type":"education","lineage":["https://openalex.org/I149481174"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinji Nakamura","raw_affiliation_strings":["Department of Electronics Engineering, Tamagawa University, Machida, Tokyo, Japan","Tamagawa Univ., Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, Tamagawa University, Machida, Tokyo, Japan","institution_ids":["https://openalex.org/I149481174"]},{"raw_affiliation_string":"Tamagawa Univ., Tokyo","institution_ids":["https://openalex.org/I149481174"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084180408","display_name":"Yasuo Nagazumi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146980","display_name":"Meguro Parasitological Museum","ror":"https://ror.org/050bkqc56","country_code":"JP","type":"archive","lineage":["https://openalex.org/I4210146980"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasuo Nagazumi","raw_affiliation_strings":["GDS, Inc., Meguro, Tokyo, Japan","GDS Inc., Meguro-ku, Tokyo, 153-0063 Japan. e-mail: nagazumi@mub.biglobe.ne.jp"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"GDS, Inc., Meguro, Tokyo, Japan","institution_ids":["https://openalex.org/I4210146980"]},{"raw_affiliation_string":"GDS Inc., Meguro-ku, Tokyo, 153-0063 Japan. e-mail: nagazumi@mub.biglobe.ne.jp","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20623267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"26","issue":null,"first_page":"732","last_page":"736"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6796959042549133},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.636437177658081},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.6050397157669067},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5728329420089722},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5499094724655151},{"id":"https://openalex.org/keywords/charge","display_name":"Charge (physics)","score":0.539868175983429},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5320863127708435},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.47953009605407715},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4694121778011322},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4635431468486786},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.45623162388801575},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4509508013725281},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4207894802093506},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.353855699300766},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.298598051071167},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2120594084262848},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19057407975196838},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.18524175882339478},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14952430129051208},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.14495325088500977},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1375025510787964},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08793872594833374}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6796959042549133},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.636437177658081},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.6050397157669067},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5728329420089722},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5499094724655151},{"id":"https://openalex.org/C188082385","wikidata":"https://www.wikidata.org/wiki/Q73792","display_name":"Charge (physics)","level":2,"score":0.539868175983429},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5320863127708435},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.47953009605407715},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4694121778011322},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4635431468486786},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.45623162388801575},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4509508013725281},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4207894802093506},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.353855699300766},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.298598051071167},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2120594084262848},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19057407975196838},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.18524175882339478},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14952430129051208},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.14495325088500977},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1375025510787964},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08793872594833374},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ciss.2007.4298403","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ciss.2007.4298403","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 41st Annual Conference on Information Sciences and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2066493139","https://openalex.org/W2080504155","https://openalex.org/W2101537171","https://openalex.org/W2113742150","https://openalex.org/W2119732736","https://openalex.org/W2152044676"],"related_works":["https://openalex.org/W2526300902","https://openalex.org/W2063209251","https://openalex.org/W2098419840","https://openalex.org/W2121963733","https://openalex.org/W2066280488","https://openalex.org/W1977171228","https://openalex.org/W2160684472","https://openalex.org/W2125567818","https://openalex.org/W4321637079","https://openalex.org/W2356714888"],"abstract_inverted_index":{"Application":[0],"examples":[1],"of":[2,13,51,63],"charge-domain":[3,14],"logic":[4],"are":[5,18,72],"described.":[6],"To":[7],"investigate":[8],"the":[9,64],"characteristics":[10],"and":[11,23,30,39],"possibilities":[12],"logic,":[15],"prototype":[16],"implementations":[17],"made":[19],"for":[20,69],"full":[21],"adder":[22],"CRC":[24],"checker":[25],"designs":[26,45,71],"by":[27,32],"standard":[28],"CMOS,":[29],"fabricated":[31],"MOSIS":[33],"1.5":[34],"mum":[35],"double":[36,40],"overlapping":[37],"poly,":[38],"metal":[41],"technology.":[42],"Those":[43],"application":[44],"require":[46],"less":[47],"than":[48],"8":[49],"steps":[50],"charge":[52],"transfer":[53],"so":[54],"that":[55],"no":[56],"special":[57],"fabrication":[58],"process":[59],"is":[60],"required.":[61],"Some":[62],"results":[65],"from":[66],"evaluation":[67],"experiment":[68],"both":[70],"also":[73],"included.":[74]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
