{"id":"https://openalex.org/W2913377581","doi":"https://doi.org/10.1109/cisp-bmei.2018.8633059","title":"Design of JESD204B Multi-Channel Data Acquisition and Playback System Based on SoPC","display_name":"Design of JESD204B Multi-Channel Data Acquisition and Playback System Based on SoPC","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2913377581","doi":"https://doi.org/10.1109/cisp-bmei.2018.8633059","mag":"2913377581"},"language":"en","primary_location":{"id":"doi:10.1109/cisp-bmei.2018.8633059","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cisp-bmei.2018.8633059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 11th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060676340","display_name":"Jiadong Yuan","orcid":null},"institutions":[{"id":"https://openalex.org/I125839683","display_name":"Beijing Institute of Technology","ror":"https://ror.org/01skt4w74","country_code":"CN","type":"education","lineage":["https://openalex.org/I125839683","https://openalex.org/I890469752"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jiadong Yuan","raw_affiliation_strings":["School of Information and Electronics, Beijing Institute of Technology, Beijing, China"],"affiliations":[{"raw_affiliation_string":"School of Information and Electronics, Beijing Institute of Technology, Beijing, China","institution_ids":["https://openalex.org/I125839683"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100660297","display_name":"Min Xie","orcid":"https://orcid.org/0000-0001-7067-5415"},"institutions":[{"id":"https://openalex.org/I125839683","display_name":"Beijing Institute of Technology","ror":"https://ror.org/01skt4w74","country_code":"CN","type":"education","lineage":["https://openalex.org/I125839683","https://openalex.org/I890469752"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Min Xie","raw_affiliation_strings":["School of Information and Electronics, Beijing Institute of Technology, Beijing, China"],"affiliations":[{"raw_affiliation_string":"School of Information and Electronics, Beijing Institute of Technology, Beijing, China","institution_ids":["https://openalex.org/I125839683"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100406622","display_name":"Siyuan Liu","orcid":"https://orcid.org/0000-0002-2142-879X"},"institutions":[{"id":"https://openalex.org/I125839683","display_name":"Beijing Institute of Technology","ror":"https://ror.org/01skt4w74","country_code":"CN","type":"education","lineage":["https://openalex.org/I125839683","https://openalex.org/I890469752"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Siyuan Liu","raw_affiliation_strings":["School of Information and Electronics, Beijing Institute of Technology, Beijing, China"],"affiliations":[{"raw_affiliation_string":"School of Information and Electronics, Beijing Institute of Technology, Beijing, China","institution_ids":["https://openalex.org/I125839683"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033794365","display_name":"Dengyue Zhai","orcid":null},"institutions":[{"id":"https://openalex.org/I125839683","display_name":"Beijing Institute of Technology","ror":"https://ror.org/01skt4w74","country_code":"CN","type":"education","lineage":["https://openalex.org/I125839683","https://openalex.org/I890469752"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dengyue Zhai","raw_affiliation_strings":["School of Information and Electronics, Beijing Institute of Technology, Beijing, China"],"affiliations":[{"raw_affiliation_string":"School of Information and Electronics, Beijing Institute of Technology, Beijing, China","institution_ids":["https://openalex.org/I125839683"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5060676340"],"corresponding_institution_ids":["https://openalex.org/I125839683"],"apc_list":null,"apc_paid":null,"fwci":0.7574,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.71926179,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.8004906177520752},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7727360725402832},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7027665376663208},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6808667778968811},{"id":"https://openalex.org/keywords/data-acquisition","display_name":"Data acquisition","score":0.6722625494003296},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6455086469650269},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6105051636695862},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5893304944038391},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.5215204358100891},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4823286235332489},{"id":"https://openalex.org/keywords/firmware","display_name":"Firmware","score":0.4706536829471588},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.42604103684425354}],"concepts":[{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.8004906177520752},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7727360725402832},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7027665376663208},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6808667778968811},{"id":"https://openalex.org/C163985040","wikidata":"https://www.wikidata.org/wiki/Q1172399","display_name":"Data acquisition","level":2,"score":0.6722625494003296},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6455086469650269},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6105051636695862},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5893304944038391},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.5215204358100891},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4823286235332489},{"id":"https://openalex.org/C67212190","wikidata":"https://www.wikidata.org/wiki/Q104851","display_name":"Firmware","level":2,"score":0.4706536829471588},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.42604103684425354},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cisp-bmei.2018.8633059","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cisp-bmei.2018.8633059","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 11th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2117241246","https://openalex.org/W2516413825","https://openalex.org/W2548697503"],"related_works":["https://openalex.org/W2371772824","https://openalex.org/W2350519679","https://openalex.org/W2169881414","https://openalex.org/W2042843335","https://openalex.org/W91163024","https://openalex.org/W2384933562","https://openalex.org/W2976906885","https://openalex.org/W176541301","https://openalex.org/W2146938890","https://openalex.org/W1602498082"],"abstract_inverted_index":{"This":[0],"paper":[1,112],"designs":[2],"a":[3],"multi-channel":[4],"data":[5,17,68],"synchronous":[6,16],"acquisition":[7,18,123],"and":[8,28,32,50,53,81,100,124,127],"playback":[9],"system":[10,63,91],"to":[11,95],"realize":[12,43],"the":[13,36,44,48,51,54,58,62,67,72,84,90,98,105,114,117,129,133],"function":[14],"of":[15,19,74,83,86,116,132],"ADC":[20],"chips,":[21],"Field":[22],"Programmable":[23,87],"Gate":[24],"Array":[25],"(FPGA)":[26],"receiving":[27],"processing":[29,125],"digital":[30],"data,":[31],"DAC":[33],"playback.":[34],"Because":[35],"high-speed":[37],"serial":[38,55],"protocol":[39],"JESD204B":[40,65],"can":[41],"easily":[42],"channel":[45],"synchronization":[46],"between":[47],"converters":[49],"FPGA,":[52],"interface":[56],"eliminates":[57],"redundant":[59],"associated":[60],"clock,":[61],"adopts":[64],"as":[66],"interface.":[69],"Based":[70],"on":[71],"characteristics":[73],"good":[75],"real-time":[76,121],"performance,":[77],"simple":[78],"structure,":[79],"flexibility":[80],"efficiency":[82],"System":[85],"Chip":[88],"(SoPC),":[89],"uses":[92],"SoPC":[93],"technology":[94],"dynamically":[96],"configure":[97],"chips":[99],"Intellectual":[101],"Property":[102],"(IP)cores":[103],"through":[104],"Microblaze":[106],"soft":[107],"core":[108],"processor.":[109],"Finally,":[110],"this":[111],"completed":[113],"construction":[115],"hardware":[118],"platform":[119],"for":[120],"signal":[122],"playback,":[126],"realized":[128],"expected":[130],"functions":[131],"system.":[134]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}