{"id":"https://openalex.org/W7161181442","doi":"https://doi.org/10.1109/cicc65509.2026.11509597","title":"A Dynamic-Active Static-Sleep 18T Flip-Flop Supporting Retentive Clock Gating in 28nm CMOS","display_name":"A Dynamic-Active Static-Sleep 18T Flip-Flop Supporting Retentive Clock Gating in 28nm CMOS","publication_year":2026,"publication_date":"2026-04-19","ids":{"openalex":"https://openalex.org/W7161181442","doi":"https://doi.org/10.1109/cicc65509.2026.11509597"},"language":null,"primary_location":{"id":"doi:10.1109/cicc65509.2026.11509597","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc65509.2026.11509597","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062397372","display_name":"Dong-Kwon Lee","orcid":"https://orcid.org/0009-0004-0318-501X"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dongkwon Lee","raw_affiliation_strings":["Seoul National University,Department of Intelligence and Information,Seoul,South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University,Department of Intelligence and Information,Seoul,South Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136123778","display_name":"Donghyun Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Donghyun Kim","raw_affiliation_strings":["Seoul National University,Department of Intelligence and Information,Seoul,South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University,Department of Intelligence and Information,Seoul,South Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053248335","display_name":"Dongsuk Jeon","orcid":"https://orcid.org/0000-0002-0395-8076"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dongsuk Jeon","raw_affiliation_strings":["Seoul National University,Department of Intelligence and Information,Seoul,South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seoul National University,Department of Intelligence and Information,Seoul,South Korea","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I139264467"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7468000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7468000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.16599999368190765,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10919","display_name":"Neurological disorders and treatments","score":0.006800000090152025,"subfield":{"id":"https://openalex.org/subfields/2728","display_name":"Neurology"},"field":{"id":"https://openalex.org/fields/27","display_name":"Medicine"},"domain":{"id":"https://openalex.org/domains/4","display_name":"Health Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48919999599456787},{"id":"https://openalex.org/keywords/field-effect-transistor","display_name":"Field-effect transistor","score":0.30559998750686646},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.29269999265670776},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.2833999991416931},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2800000011920929}],"concepts":[{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.5860000252723694},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48919999599456787},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.45660001039505005},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3880000114440918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.34380000829696655},{"id":"https://openalex.org/C145598152","wikidata":"https://www.wikidata.org/wiki/Q176097","display_name":"Field-effect transistor","level":4,"score":0.30559998750686646},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2962000072002411},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.29269999265670776},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.2833999991416931},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2800000011920929},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.26260000467300415},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.2624000012874603},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.25850000977516174}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc65509.2026.11509597","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc65509.2026.11509597","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7075492739677429}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322120","display_name":"National Research Foundation of Korea","ror":"https://ror.org/013aysd81"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,14,18,23],"dynamic-active":[4],"static-sleep":[5],"18T":[6],"flip-flop":[7],"that":[8],"provides":[9],"retentive":[10],"clock":[11],"gating,":[12],"employing":[13],"hybrid":[15],"structure":[16],"with":[17],"dynamic":[19,57],"primary":[20],"latch":[21],"and":[22,37,43],"static":[24,49],"single-phase":[25],"clocked":[26],"secondary":[27],"latch.":[28],"Fabricated":[29],"in":[30],"28nm":[31],"FD-SOI,":[32],"it":[33,60],"consumes":[34],"1.59":[35],"fJ/cycle":[36],"achieves":[38],"46%":[39],"lower":[40],"power-delay":[41],"product":[42],"6%":[44],"smaller":[45],"area":[46],"than":[47],"recent":[48],"designs":[50],"while":[51],"closely":[52],"matching":[53],"prior":[54],"clock-gating-incompatible":[55],"low-power":[56,66],"flip-flops,":[58],"making":[59],"an":[61],"ideal":[62],"candidate":[63],"for":[64],"clock-gated":[65],"digital":[67],"systems.":[68]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2026-05-15T00:00:00"}