{"id":"https://openalex.org/W7161175586","doi":"https://doi.org/10.1109/cicc65509.2026.11509587","title":"A 0.039mm <sup>2</sup> Temperature-Robust 7.2GHz Fractional-N RO-PLL Achieving 257.9fs <sub>rms</sub> Jitter and \u2212255.5dB FoM <sub>N</sub>","display_name":"A 0.039mm <sup>2</sup> Temperature-Robust 7.2GHz Fractional-N RO-PLL Achieving 257.9fs <sub>rms</sub> Jitter and \u2212255.5dB FoM <sub>N</sub>","publication_year":2026,"publication_date":"2026-04-19","ids":{"openalex":"https://openalex.org/W7161175586","doi":"https://doi.org/10.1109/cicc65509.2026.11509587"},"language":null,"primary_location":{"id":"doi:10.1109/cicc65509.2026.11509587","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc65509.2026.11509587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5136133707","display_name":"Haoran Li","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Haoran Li","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078356928","display_name":"J li","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Jinge Li","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136149704","display_name":"Shangmin Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Shangmin Yu","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079201910","display_name":"Xiaoqi Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Xiaoqi Lin","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136135436","display_name":"Xueying Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Xueying Jiang","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062261926","display_name":"Xi Meng","orcid":"https://orcid.org/0000-0002-2320-5012"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Xi Meng","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136121277","display_name":"Pui-In Mak","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Pui-In Mak","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136102790","display_name":"Rui Paulo Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5136166592","display_name":"Jun Yin","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Jun Yin","raw_affiliation_strings":["University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,China","institution_ids":["https://openalex.org/I204512498"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.7101089,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.7182999849319458,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.7182999849319458,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.10279999673366547,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10232","display_name":"Optical Network Technologies","score":0.03799999877810478,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.3025999963283539},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.29829999804496765},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.2743000090122223},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.2531999945640564}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42649999260902405},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40220001339912415},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3828999996185303},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3361999988555908},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.3025999963283539},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30239999294281006},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.29829999804496765},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.2743000090122223},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.2531999945640564},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.24160000681877136}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc65509.2026.11509587","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc65509.2026.11509587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320337495","display_name":"Technology Development","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,12,17,28,33,83],"low-jitter,":[4],"low-spur,":[5],"and":[6,32,41,48,67],"temperature-robust":[7],"ring-oscillator-based":[8],"PLL":[9],"(RO-PLL)":[10],"in":[11,60],"compact":[13],"area.":[14],"It":[15],"exploits":[16],"complementary":[18],"SPD":[19],"(C-SPD)":[20],"to":[21,44,97],"reduce":[22],"the":[23,49,76,90,95],"reference":[24],"(REF)":[25],"spur":[26,109],"through":[27],"differential":[29],"sampling":[30],"scheme,":[31],"current-interpolation":[34],"DTC":[35],"(CI-DTC)":[36],"with":[37],"its":[38],"non-linearity":[39],"(NL)":[40],"gain":[42],"insensitive":[43],"changes":[45],"of":[46,72,87],"temperature":[47,100],"PLL\u2019s":[50],"output":[51],"frequency,":[52],"thereby":[53],"avoiding":[54],"background":[55],"NL":[56],"calibration.":[57],"The":[58,106],"RO-PLL":[59],"28nm":[61],"CMOS":[62],"occupies":[63],"0.039mm<sup":[64],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[65],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[66],"measures":[68],"an":[69],"integrated":[70],"jitter":[71,92],"257.9":[73],"fs":[74],"at":[75],"near-integer":[77],"fractional-N":[78],"channel":[79],"around":[80],"7.2GHz.":[81],"After":[82],"one-time":[84],"foreground":[85],"calibration":[86],"CI-DTC\u2019s":[88],"NL,":[89],"measured":[91,107],"degradation":[93],"across":[94],"\u221220":[96],"100":[98],"\u00b0C":[99],"range":[101],"is":[102,110],"kept":[103],"below":[104],"11%.":[105],"REF":[108],"\u221267.7":[111],"dBc.":[112]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2026-05-15T00:00:00"}