{"id":"https://openalex.org/W7161152480","doi":"https://doi.org/10.1109/cicc65509.2026.11509537","title":"A 1.6-to-16 GHz Sub-1-LSB INL <sub>pp</sub> 7-bit Phase Interpolator Using Constant-Load Unit with Trimming-Free Digital Calibration in 28-nm CMOS","display_name":"A 1.6-to-16 GHz Sub-1-LSB INL <sub>pp</sub> 7-bit Phase Interpolator Using Constant-Load Unit with Trimming-Free Digital Calibration in 28-nm CMOS","publication_year":2026,"publication_date":"2026-04-19","ids":{"openalex":"https://openalex.org/W7161152480","doi":"https://doi.org/10.1109/cicc65509.2026.11509537"},"language":null,"primary_location":{"id":"doi:10.1109/cicc65509.2026.11509537","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc65509.2026.11509537","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101827861","display_name":"Xianting Su","orcid":"https://orcid.org/0009-0009-1403-7094"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xianting Su","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003457423","display_name":"Xiaoteng Zhao","orcid":"https://orcid.org/0000-0002-9447-8763"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoteng Zhao","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136135509","display_name":"Zekai Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zekai Yang","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004631913","display_name":"Zhicheng Dong","orcid":"https://orcid.org/0009-0005-3584-1453"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhicheng Dong","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003485495","display_name":"MF Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Miao Zhang","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136186499","display_name":"Jie Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jie Liu","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012380614","display_name":"Hongyu Su","orcid":"https://orcid.org/0009-0005-8334-8743"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hongyu Su","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136140494","display_name":"Bowen Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bowen Wang","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5136162975","display_name":"Shubin Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shubin Liu","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5136158451","display_name":"Zhangming Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhangming Zhu","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems,Xi'an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5101827861"],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.9090495,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.5159000158309937,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.5159000158309937,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.2809999883174896,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.12929999828338623,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.6302000284194946},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4708000123500824},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.3855000138282776},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.33390000462532043},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.289900004863739}],"concepts":[{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.6302000284194946},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4708000123500824},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45249998569488525},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44119998812675476},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.3855000138282776},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.37599998712539673},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37400001287460327},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.33390000462532043},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30869999527931213},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.289900004863739},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.25999999046325684}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc65509.2026.11509537","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc65509.2026.11509537","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8438142538070679}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,31,72,88,125],"7-bit":[4],"current-mode":[5],"phase":[6],"interpolator":[7],"(PI)":[8],"characterized":[9],"by":[10],"high":[11],"linearity,":[12],"wide":[13],"operation":[14],"range,":[15],"low":[16],"jitter,":[17],"and":[18,41,48,69,135],"compact":[19],"area.":[20],"The":[21],"proposed":[22,115],"PI":[23,116],"utilizes":[24],"constant-load":[25],"units":[26],"(CLUs)":[27],"in":[28,45,81],"synergy":[29],"with":[30,101],"trimming-free":[32],"digital":[33,49],"calibration,":[34],"suppressing":[35],"the":[36,53,57,59,85,114],"nonlinearity":[37,92,128],"from":[38,144],"circuit":[39],"non-idealities":[40],"systematic":[42],"interpolation":[43],"error":[44],"both":[46],"analog":[47],"domains.":[50],"Thanks":[51],"to":[52,147],"balanced":[54],"topology":[55],"of":[56,104,122,132,139],"CLU,":[58],"input":[60,76],"load":[61],"variation":[62,78],"is":[63],"13.5\u00d7":[64],"less":[65],"than":[66,74],"conventional":[67],"unit":[68],"thus":[70],"achieves":[71,87,117],"more":[73],"7\u00d7":[75],"amplitude":[77],"reduction.":[79],"Fabricated":[80],"28-nm":[82],"CMOS":[83],"technology,":[84],"prototype":[86],"sub-1-LSB":[89],"peak-to-peak":[90,126],"integral":[91],"(INL<inf":[93],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[94,107,120,130,142],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">pp</inf>)":[95,131],"over":[96],"10:1":[97],"relative":[98],"bandwidth":[99],"(1.6~16GHz)":[100],"an":[102,118,136],"area":[103],"3490":[105],"\u03bcm<sup":[106],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>.":[108],"When":[109],"operating":[110],"at":[111],"8":[112],"GHz,":[113,149],"INL<inf":[119],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">pp</inf>":[121],"0.79":[123],"LSB,":[124,134],"differential":[127],"(DNL<inf":[129],"0.95":[133],"integrated":[137],"jitter":[138],"34.55":[140],"fs<inf":[141],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">rms</inf>":[143],"10":[145],"kHz":[146],"1":[148],"while":[150],"consuming":[151],"5.83":[152],"mW":[153],"power.":[154]},"counts_by_year":[],"updated_date":"2026-05-16T06:04:12.930555","created_date":"2026-05-15T00:00:00"}
